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    TESTING AND REPAIR OF A HARDWARE ACCELERATOR IMAGE IN A PROGRAMMABLE LOGIC CIRCUIT
    11.
    发明申请
    TESTING AND REPAIR OF A HARDWARE ACCELERATOR IMAGE IN A PROGRAMMABLE LOGIC CIRCUIT 有权
    可编程逻辑电路中硬件加速器图像的测试和修复

    公开(公告)号：US20150339130A1

    公开(公告)日：2015-11-26

    申请号：US14360657

    申请日：2013-02-19

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Ezekiel KRUGLICK

    IPC: G06F9/445 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F9/44505 ,  G01R31/318519 ,  G06F11/277 ,  G06F11/3024 ,  G06F11/3409

    Abstract: Techniques described herein generally include methods for the testing and repair of a hardware accelerator image in a programmable logic circuit. In a processor chip that includes multiple programmable logic circuits, a hardware accelerator image programmed into a first programmable logic circuit is tested by programming a testing circuit with a duplicate hardware accelerator image and bringing the testing circuit to the same logic state as the first programmable logic circuit. Comparing outputs from the first programmable logic circuit and the testing circuit indicates the accuracy of the hardware accelerator image programmed into the first programmable logic circuit. The testing circuit may replace the first programmable logic circuit, or the testing circuit may be reprogrammed for testing other hardware accelerator images programmed into other programmable logic circuits of the processor chip.

    Abstract translation: 本文描述的技术通常包括用于在可编程逻辑电路中测试和修复硬件加速器图像的方法。 在包括多个可编程逻辑电路的处理器芯片中，通过用复制硬件加速器图像编程测试电路并将测试电路与第一可编程逻辑相同的逻辑状态来测试编程到第一可编程逻辑电路中的硬件加速器图像 电路。 比较来自第一可编程逻辑电路和测试电路的输出指示编程到第一可编程逻辑电路中的硬件加速器图像的精度。 测试电路可以替换第一可编程逻辑电路，或者可以对测试电路进行重新编程，以测试编程到处理器芯片的其他可编程逻辑电路中的其他硬件加速器图像。

    VERIFICATION LOCATION DETERMINATION FOR ENTITY PRESENCE CONFIRMATION OF ONLINE PURCHASES
    13.
    发明申请
    VERIFICATION LOCATION DETERMINATION FOR ENTITY PRESENCE CONFIRMATION OF ONLINE PURCHASES 审中-公开
    验证位置确定实体存在确认在线购买

    公开(公告)号：US20160292687A1

    公开(公告)日：2016-10-06

    申请号：US14438223

    申请日：2014-10-13

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Ezekiel KRUGLICK

    IPC: G06Q20/40 ,  H04W4/02 ,  G06Q20/32

    CPC classification number: G06Q20/4016 ,  G06Q20/12 ,  G06Q20/3224 ,  H04W4/021

    Abstract: Technologies are generally described that relate to verification location determination for entity presence confirmation of online purchases. An example method may include determining whether a first risk level associated with a first candidate transaction is capable of mitigation to a defined level via physical verification of an entity associated with the first candidate transaction, wherein the first candidate transaction is determined to satisfy a defined risk profile. The method may also include, in response to determining that the first risk level associated with the first candidate transaction is capable of the mitigation to the defined level via the physical verification, generating location information indicative of a selected location for the physical verification.

    Abstract translation: 通常描述与用于在线购买的实体存在确认的验证位置确定相关的技术。 示例性方法可以包括确定与第一候选交易相关联的第一风险级别是否能够通过与第一候选交易相关联的实体的物理验证来缓解到定义的级别，其中确定第一候选交易以满足定义的风险 个人资料 该方法还可以包括响应于确定与第一候选事务相关联的第一风险级别能够经由物理验证来缓解到所定义的级别，生成指示用于物理验证的选定位置的位置信息。

    MIGRATION OF EXECUTING PROCESSES
    14.
    发明申请
    MIGRATION OF EXECUTING PROCESSES 审中-公开
    执行过程的移交

    公开(公告)号：US20160216951A1

    公开(公告)日：2016-07-28

    申请号：US14379630

    申请日：2013-08-08

    Applicant: Empire Technology Development LLC

    Inventor： Ezekiel KRUGLICK ,  Kevin S. FINE

    IPC: G06F9/45 ,  G06F9/30

    CPC classification number: G06F8/41 ,  G06F9/30145 ,  G06F9/4552 ,  G06F15/80

    Abstract: In one example embodiment, live migration in a datacenter may include JIT compiling a process that is configured to be executed on both a source instruction set architecture and a destination instruction set architecture, mapping variables and address stacks of the process on both the source instruction set architecture and the destination instruction set architecture into a labeled form thereof, and mapping the labeled form of the variables and address stacks onto the destination instruction set architecture.

    Abstract translation: 在一个示例实施例中，数据中心中的实时迁移可以包括JIT编译被配置为在源指令集架构和目的地指令集架构两者上执行的进程，在源指令集上映射变量和处理的地址栈 架构和目的地指令集架构变成其标记形式，并将变量和地址栈的标记形式映射到目标指令集架构上。

    TRACKING CORE-LEVEL INSTRUCTION SET CAPABILITIES IN A CHIP MULTIPROCESSOR
    15.
    发明申请
    TRACKING CORE-LEVEL INSTRUCTION SET CAPABILITIES IN A CHIP MULTIPROCESSOR 有权
    跟踪芯片级多媒体指令集的能力

    公开(公告)号：US20160019130A1

    公开(公告)日：2016-01-21

    申请号：US14396058

    申请日：2013-06-18

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Ezekiel KRUGLICK

    IPC: G06F11/34 ,  G06F9/48 ,  G06F11/30 ,  G06F11/20

    CPC classification number: G06F11/3409 ,  G06F9/4806 ,  G06F9/5044 ,  G06F11/2033 ,  G06F11/3024

    Abstract: Techniques described herein generally relate to a task management system for a chip multiprocessor having multiple processor cores. The task management system tracks the changing instruction set capabilities of each processor core and selects processor cores for use based on the tracked capabilities. In this way, a processor core with one or more failed processing elements can still be used effectively, since the processor core may be selected to process instruction sets that do not use the failed processing elements.

    Abstract translation: 本文描述的技术通常涉及具有多个处理器核的芯片多处理器的任务管理系统。 任务管理系统跟踪每个处理器核心的改变的指令集能力，并根据跟踪的能力选择使用的处理器核心。 以这种方式，仍然可以有效地使用具有一个或多个失败的处理元件的处理器核心，因为可以选择处理器核来处理不使用失败的处理元件的指令集。

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