Bus structure for parallel connected power switches

    公开(公告)号:US11056860B2

    公开(公告)日:2021-07-06

    申请号:US16599955

    申请日:2019-10-11

    Abstract: An apparatus includes a plurality of semiconductor switches. A first bus interconnects first terminals of the semiconductor switches in a first chain and provides a first impedance between the first terminals of switches of the first chain. A second bus interconnects second terminals of the semiconductor switches in a second chain and provides a second impedance greater that the first impedance between the second terminals of the switches of the second chain. The apparatus may be implemented as a laminated bus assembly including respective overlapping conductor plates, wherein the second bus includes a plate having subregions defined by features, such as slots or grooves, that provide the second impedance.

    BUS BAR ASSEMBLY WITH INTEGRATED SURGE ARRESTOR

    公开(公告)号:US20210202141A1

    公开(公告)日:2021-07-01

    申请号:US16989531

    申请日:2020-08-10

    Abstract: An apparatus includes a laminated bus bar assembly with first and second bus bars and an intervening insulator layer. A surge arrestor (e.g., a metal oxide varistor) has a body mounted on the bus bar assembly and first and second terminals on first and second opposite sides of the body. In some embodiments, the body may be at least partially disposed in an opening in the first bus bar and the second terminal may be conductively bonded to a surface of the second bus bar that faces the insulator layer. In some embodiments, the second terminal may include a conductive stud passing through an opening in the second bus bar. The apparatus may include a spring clamp attached to the first bus bar and contacting the first side of the body to retain the body.

    BUS STRUCTURE FOR PARALLEL CONNECTED POWER SWITCHES

    公开(公告)号:US20210111542A1

    公开(公告)日:2021-04-15

    申请号:US16599955

    申请日:2019-10-11

    Abstract: An apparatus includes a plurality of semiconductor switches. A first bus interconnects first terminals of the semiconductor switches in a first chain and provides a first impedance between the first terminals of switches of the first chain. A second bus interconnects second terminals of the semiconductor switches in a second chain and provides a second impedance greater that the first impedance between the second terminals of the switches of the second chain. The apparatus may be implemented as a laminated bus assembly including respective overlapping conductor plates, wherein the second bus includes a plate having subregions defined by features, such as slots or grooves, that provide the second impedance.

    Low-Impedance Bus Assemblies and Apparatus Including the Same

    公开(公告)号:US20200273792A1

    公开(公告)日:2020-08-27

    申请号:US16797039

    申请日:2020-02-21

    Abstract: A bus assembly includes a planar first bus, a second bus including a first planar bus section on the first bus and a second planar bus section connected to the first planar bus section and offset from the first planar bus section, and a third bus comprising a third planar bus section disposed between the first bus and the second planar bus section, and a fourth planar bus section connected to the third planar bus section, offset from third planar bus section, and disposed on the first planar bus section.

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