公开(公告)号：US08546199B2

公开(公告)日：2013-10-01

申请号：US13792436

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L21/336

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US08546198B2

公开(公告)日：2013-10-01

申请号：US13792395

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L21/336

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US09299758B2

公开(公告)日：2016-03-29

申请号：US13960413

申请日：2013-08-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Hee Park ,  Chi Sun Hwang

IPC: H01L27/32 ,  H01L51/52 ,  G02F1/1335

CPC classification number: H01L27/3267 ,  G02F1/133553 ,  G02F2001/133626 ,  H01L51/5271

Abstract: Disclosed is a dual display device having a vertical structure, in which a reflective display device and a self-emissive display device are formed on one substrate in a vertical structure so as to enable a reflective display or a self-emissive display according to a situation and provide a high resolution display. The dual display device having a vertical structure includes: a thin film transistor formed on a substrate; a white light emitting device formed on the thin film transistor: a reflection adjusting layer formed on the white light emitting device; and a color converting layer formed on the reflection adjusting layer.

Abstract translation: 公开了一种具有垂直结构的双显示装置，其中反射显示装置和自发光显示装置以垂直结构形成在一个基板上，以便能够根据情况进行反射显示或自发显示 并提供高分辨率显示。 具有垂直结构的双显示装置包括：形成在基板上的薄膜晶体管; 形成在所述薄膜晶体管上的白色发光器件，形成在所述白色发光器件上的反射调节层; 以及形成在反射调节层上的颜色转换层。

公开(公告)号：US20140035622A1

公开(公告)日：2014-02-06

申请号：US14050313

申请日：2013-10-09

Applicant: Konkuk University Industrial Cooperation Corp ,  ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sang Hee PARK ,  Chi Sun Hwang ,  Sung Min Yoon ,  Him Chan Oh ,  Kee Chan Park ,  Tao Ren ,  Hong Kyun Leem ,  Min Woo Oh ,  Ji Sun Kim ,  Jae Eun Pi ,  Byeong Hoon Kim ,  Byoung Gon Yu

IPC: H03K19/094

CPC classification number: H03K3/012 ,  H03K19/094 ,  H03K19/20

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.