公开(公告)号：US08841665B2

公开(公告)日：2014-09-23

申请号：US13849111

申请日：2013-03-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Hee Park ,  Min Ki Ryu ,  Him Chan Oh ,  Chi Sun Hwang

IPC: H01L21/16 ,  H01L21/76 ,  H01L21/00 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66742

Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.

Abstract translation: 公开了一种制造氧化物薄膜晶体管的方法，包括：在其上形成有缓冲层的基板上形成栅电极; 在其上形成有栅电极的基板的整个表面上形成栅极绝缘层; 在所述栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一蚀刻停止层; 通过原子层沉积法在第一蚀刻停止层上形成第二蚀刻停止层; 在第一蚀刻停止层和第二蚀刻停止层中形成第一蚀刻停止层和第二蚀刻停止层，或形成暴露氧化物半导体层的一部分的接触孔; 在所述第一蚀刻停止层和所述第二蚀刻停止层上形成源电极和漏电极; 以及在其上形成有源电极和漏电极的基板的整个表面上形成钝化层。

公开(公告)号：US08749300B2

公开(公告)日：2014-06-10

申请号：US13633654

申请日：2012-10-02

Applicant: Electronics and Telecommunications Research Institute ,  Konkuk University Industrial Cooperation Corp

Inventor： Jae Eun Pi ,  Kee Chan Park ,  Hong Kyun Leem ,  Joon Dong Kim ,  Youn Kyung Kim ,  Ji Sun Kim ,  Byoung Gon Yu ,  Sang Hee Park ,  Him Chan Oh ,  Min Ki Ryu ,  Chi Sun Hwang

IPC: G05F1/10 ,  H02M3/07

CPC classification number: H02M3/073 ,  G09G3/3696 ,  H02M2003/077

Abstract: Disclosed is a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto.

Abstract translation: 公开了一种液晶显示装置的DC电压转换电路，包括：主泵浦电路，其包括多个薄膜晶体管，并且被配置为当多个薄膜晶体管交替接通时输出用于驱动液晶显示装置的电压 或关闭 以及开关控制信号发生器，其被配置为通过反转时钟信号来控制施加到所述多个薄膜晶体管的栅极的电压，其中当施加正栅极 - 源极电压时，每个薄膜晶体管导通，并且当所述薄膜晶体管被施加到其上时截止， 对其施加负栅极 - 源极电压。

公开(公告)号：US20130264564A1

公开(公告)日：2013-10-10

申请号：US13849111

申请日：2013-03-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Hee Park ,  Min Ki Ryu ,  Him Chan Oh ,  Chi Sun Hwang

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66742

Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.

Abstract translation: 公开了一种制造氧化物薄膜晶体管的方法，包括：在其上形成有缓冲层的基板上形成栅电极; 在其上形成有栅电极的基板的整个表面上形成栅极绝缘层; 在所述栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一蚀刻停止层; 通过原子层沉积法在第一蚀刻停止层上形成第二蚀刻停止层; 在第一蚀刻停止层和第二蚀刻停止层中形成第一蚀刻停止层和第二蚀刻停止层，或形成暴露氧化物半导体层的一部分的接触孔; 在所述第一蚀刻停止层和所述第二蚀刻停止层上形成源电极和漏电极; 以及在其上形成有源电极和漏电极的基板的整个表面上形成钝化层。

公开(公告)号：US09245978B2

公开(公告)日：2016-01-26

申请号：US13960352

申请日：2013-08-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chi Sun Hwang ,  Sang Hee Park ,  Him Chan Oh

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.

Abstract translation: 公开了一种在具有自对准结构的薄膜晶体管中使用掺杂阻挡层控制掺杂材料的扩散长度的自对准薄膜晶体及其制造方法。 具有掺杂势垒的自对准薄膜晶体管包括：形成在衬底上并具有第一掺杂区，第二掺杂区和沟道区的有源层; 形成在沟道区上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述第一掺杂区域和所述第二掺杂区域上的掺杂源膜; 以及在掺杂源膜和第一掺杂区之间以及在掺杂源膜和第二掺杂区之间形成的掺杂势垒。

公开(公告)号：US20130189815A1

公开(公告)日：2013-07-25

申请号：US13792395

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki RYU ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

Abstract translation: 一种制造透明晶体管的方法，所述透明晶体管包括形成在所述基板上的基板，源极和漏极，每个具有下透明层，金属层和上透明层的多层结构，在所述源极和漏极之间形成的沟道 电极和与通道对准的栅电极。 下透明层或上透明层由与通道相同的透明半导体层形成。

公开(公告)号：US09099991B2

公开(公告)日：2015-08-04

申请号：US14049800

申请日：2013-10-09

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  Konkuk University Industrial Cooperation Corp

Inventor： Sang Hee Park ,  Chi Sun Hwang ,  Sung Min Yoon ,  Him Chan Oh ,  Kee Chan Park ,  Tao Ren ,  Hong Kyung Leem ,  Min Woo Oh ,  Ji Sun Kim ,  Jae Eun Pi ,  Byeong Hoon Kim ,  Byoung Gon Yu

IPC: H03K19/20 ,  H03K19/094 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K19/094 ,  H03K19/20

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract translation: 公开了一种逆变器，NAND门和NOR门。 逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。

公开(公告)号：US09252241B2

公开(公告)日：2016-02-02

申请号：US14031100

申请日：2013-09-19

Applicant: Electronics and Telecommunications Research Institute

Inventor： Him Chan Oh ,  Chi Sun Hwang ,  Sang Hee Park

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/45

CPC classification number: H01L29/78696 ,  H01L29/24 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

Abstract translation: 本发明公开了一种自对准薄膜晶体管及其制造方法，其能够同时提高操作速度和稳定性，并且通过形成源极和漏极以自对准地使其尺寸最小化。 根据本公开的示例性实施例的制造薄膜晶体管的方法包括：在衬底上形成有源层，栅极绝缘体和栅极层; 形成用于限定所述栅极层上的栅电极的形状的光致抗蚀剂层图案; 通过使用光致抗蚀剂层图案蚀刻栅极层，栅极绝缘体和有源层; 通过具有方向性的沉积方法在蚀刻的衬底上沉积源极和漏极层; 以及通过去除光致抗蚀剂层图案形成栅电极和自对准源电极和漏电极。

公开(公告)号：US20140145180A1

公开(公告)日：2014-05-29

申请号：US14031100

申请日：2013-09-19

Applicant: Electronics and Telecommunications Research Institute

Inventor： Him Chan Oh ,  Chi Sun Hwang ,  Sang Hee Park

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/24 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

Abstract translation: 本发明公开了一种自对准薄膜晶体管及其制造方法，其能够同时提高操作速度和稳定性，并且通过形成源极和漏极以自对准地使其尺寸最小化。 根据本公开的示例性实施例的制造薄膜晶体管的方法包括：在衬底上形成有源层，栅极绝缘体和栅极层; 形成用于限定所述栅极层上的栅电极的形状的光致抗蚀剂层图案; 通过使用光致抗蚀剂层图案蚀刻栅极层，栅极绝缘体和有源层; 通过具有方向性的沉积方法在蚀刻的衬底上沉积源极和漏极层; 以及通过去除光致抗蚀剂层图案形成栅电极和自对准源电极和漏电极。

公开(公告)号：US08716035B2

公开(公告)日：2014-05-06

申请号：US14022705

申请日：2013-09-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Min Yoon ,  Chun Won Byun ,  Shin Hyuk Yang ,  Sang Hee Park ,  Soon Won Jung ,  Seung Youl Kang ,  Chi Sun Hwang ,  Byoung Gon Yu

IPC: H01L51/00

CPC classification number: H01L29/6684 ,  B82Y10/00 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/78391

Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.

Abstract translation: 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。

公开(公告)号：US08710866B2

公开(公告)日：2014-04-29

申请号：US14050313

申请日：2013-10-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Hee Park ,  Chi Sun Hwang ,  Sung Min Yoon ,  Him Chan Oh ,  Kee Chan Park ,  Tao Ren ,  Hong Kyun Leem ,  Min Woo Oh ,  Ji Sun Kim ,  Jae Eun Pi ,  Byeong Hoon Kim ,  Byoung Gon Yu

IPC: H03K19/20

CPC classification number: H03K3/012 ,  H03K19/094 ,  H03K19/20

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract translation: 公开了一种逆变器，NAND门和NOR门。 逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。