公开(公告)号：US06888247B2

公开(公告)日：2005-05-03

申请号：US09971471

申请日：2001-10-05

Applicant: Ellis Lee ,  Tsing-Fong Hwang

Inventor： Ellis Lee ,  Tsing-Fong Hwang

IPC: H01L21/768 ,  H01L27/04

CPC classification number: H01L21/76829 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76897

Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer As a result, the first structured dielectric layer has a substantially planar surface A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer. The first structured dielectric layer and the second structured dielectric layer also have an opening to expose the conductive structure. When the opening is shifted to the gap region between the first conductive structure and the second conductive structure due to misalignment, the portion of the opening above the gap region stops on the anti-etch layer without opening the void.

Abstract translation: 在基板上形成互连。 导电结构至少包括在其间具有间隙区域的第一导电结构和第二导电结构。 衬底在间隙区域暴露。 第一结构化介电层形成在衬底上以覆盖第一和第二导电结构。 第一结构化介电层在第一和第二导电结构之间的间隙区域也具有空隙。 空隙显着延伸到整个间隙区域。 第一结构化介电层还在空隙上方具有凹陷区域。 抗蚀刻层填充第一结构化电介质层的凹陷区域结果，第一结构化介电层具有基本上平坦的表面。第一结构化介电层和抗蚀刻层上形成有第二结构化介电层。 第一结构化介电层和第二结构化介电层也具有露出导电结构的开口。 当开口由于未对准而移动到第一导电结构和第二导电结构之间的间隙区域时，间隙区域上方的开口部分停止在抗蚀刻层上而不打开空隙。

公开(公告)号：US06245635B1

公开(公告)日：2001-06-12

申请号：US09203042

申请日：1998-11-30

Applicant: Ellis Lee

Inventor： Ellis Lee

IPC: H01L2176

CPC classification number: H01L21/76229

Abstract: A method of fabricating a shallow trench isolation includes formation of a polishing stop layer. The polishing stop layer is formed in a fill material by performing ion implantation to implant atoms in the fill material. The depth of the polishing stop layer can be controlled by the energy of the implanted atoms. The polishing stop layer prevents the fill material from being dished by chemical-mechanical polishing. The polishing stop layer also prevents scratches from forming in the surface of the fill material, which is used to form isolation regions.

Abstract translation: 制造浅沟槽隔离的方法包括形成抛光停止层。 抛光停止层通过进行离子注入而在填充材料中形成，以在填充材料中注入原子。 抛光停止层的深度可以通过注入原子的能量来控制。 抛光停止层防止填充材料通过化学机械抛光而抛光。 抛光停止层还防止在用于形成隔离区域的填充材料的表面中形成划痕。

公开(公告)号：US06171960B2

公开(公告)日：2001-01-09

申请号：US09057812

申请日：1998-04-09

Applicant: Ellis Lee

Inventor： Ellis Lee

IPC: H01L2144

CPC classification number: H01L21/76867 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating copper interconnection is provided comprising forming a dielectric layer with a trench or a via on a semiconductor substrate. A titanium layer is formed on the dielectric layer. A copper layer doped with light silicon is formed in the trench or the via. The copper layer is encapsulated by annealing to make silicon doped in the copper layer diffuse toward the surface of the copper to react with the titanium layer and the gas. It prevents the copper layer from oxidation and diffusion to increase the yield.

Abstract translation: 提供一种制造铜互连的方法，包括在半导体衬底上形成具有沟槽或通孔的电介质层。 在电介质层上形成钛层。 在沟槽或通孔中形成掺杂有硅的铜层。 通过退火对铜层进行封装，使得在铜层中掺杂的硅向铜表面扩散以与钛层和气体反应。 它防止铜层氧化和扩散以提高产率。