PACKED ROTATE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    12.
    发明申请
    PACKED ROTATE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    包装旋转处理器,方法,系统和指令

    公开(公告)号:US20140040604A1

    公开(公告)日:2014-02-06

    申请号:US13977229

    申请日:2011-12-30

    IPC分类号: G06F9/30

    CPC分类号: G06F9/30032 G06F9/30036

    摘要: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.

    摘要翻译: 一种方面的方法包括接收掩蔽的包装旋转指令。 指示指示包括多个打包数据元素的第一源打包数据,具有多个掩码元素的打包数据操作掩码,至少一个旋转量和目的地存储位置。 响应于该指令,结果打包数据被存储在目的地存储位置。 结果打包数据包括每个对应于相应相对位置中的不同掩模元素的结果数据元素。 未被对应的掩码元素掩蔽的结果数据元素包括在已经旋转的对应位置中的第一源打包数据的数据元素中的一个。 由相应的掩码元素屏蔽的结果数据元素包括一个被屏蔽的值。 公开了其它方法,装置,系统和指令。

    PACKED DATA OPERATION MASK REGISTER ARITHMETIC COMBINATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    14.
    发明申请
    PACKED DATA OPERATION MASK REGISTER ARITHMETIC COMBINATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    包装数据操作面板寄存器算术组合处理器,方法,系统和指令

    公开(公告)号:US20130275728A1

    公开(公告)日:2013-10-17

    申请号:US13976885

    申请日:2011-12-22

    IPC分类号: G06F9/30

    摘要: A method of an aspect includes receiving a packed data operation mask register arithmetic combination instruction. The packed data operation mask register arithmetic combination instruction indicates a first packed data operation mask register, indicates a second packed data operation mask register, and indicates a destination storage location. An arithmetic combination of at least a portion of bits of the first packed data operation mask register and at least a corresponding portion of bits of the second packed data operation mask register is stored in the destination storage location in response to the packed data operation mask register arithmetic combination instruction. Other methods, apparatus, systems, and instructions are disclosed.

    摘要翻译: 一种方面的方法包括接收压缩数据操作屏蔽寄存器算术组合指令。 打包数据操作屏蔽寄存器算术组合指令指示第一打包数据操作屏蔽寄存器,指示第二打包数据操作屏蔽寄存器,并指示目的地存储位置。 响应于打包数据操作屏蔽寄存器,将第一打包数据操作屏蔽寄存器的位的至少一部分与第二打包数据操作屏蔽寄存器的位的至少相应部分的算术组合存储在目的地存储位置中 算术组合指令。 公开了其它方法,装置,系统和指令。

    INSTRUCTION EXECUTION UNIT THAT BROADCASTS DATA VALUES AT DIFFERENT LEVELS OF GRANULARITY
    16.
    发明申请
    INSTRUCTION EXECUTION UNIT THAT BROADCASTS DATA VALUES AT DIFFERENT LEVELS OF GRANULARITY 有权
    指定执行单位在不同级别的范围内广播数据值

    公开(公告)号:US20130339664A1

    公开(公告)日:2013-12-19

    申请号:US13976003

    申请日:2011-12-23

    IPC分类号: G06F9/30

    摘要: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The first data structure is four times as large as the second data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second instruction to create a second replication data structure.

    摘要翻译: 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间,用于在执行第一指令时存储要复制的第一数据结构,并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 第一个数据结构是第二个数据结构的四倍。 执行单元还包括复制逻辑电路,以在执行第一指令以创建第一复制数据结构时复制第一数据结构,并且在执行第二指令以创建第二复制数据结构时复制第二数据结构。

    INSTRUCTION AND LOGIC TO PROVIDE CONVERSIONS BETWEEN A MASK REGISTER AND A GENERAL PURPOSE REGISTER OR MEMORY
    19.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE CONVERSIONS BETWEEN A MASK REGISTER AND A GENERAL PURPOSE REGISTER OR MEMORY 审中-公开
    指令和逻辑提供掩码寄存器与一般用途寄存器或存储器之间的转换

    公开(公告)号:US20150113246A1

    公开(公告)日:2015-04-23

    申请号:US13977732

    申请日:2011-11-25

    IPC分类号: G06F9/30

    摘要: Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.

    摘要翻译: 指令和逻辑在掩码寄存器和通用寄存器或存储器之间提供转换。 一些实施例,响应于指定目的地操作数,对应于多个掩码数据字段的掩码长度和源操作数的指令; 从源操作数的数据字段读取值,该数据字段对应于指定的掩码长度,并存储到由指令指定的目标操作数中的相应数据字段,其中源操作数或目标操作数中的一个是掩码寄存器。 指示屏蔽矢量元素的值可以被存储到目的地操作数中除了对应于指定掩码长度的数据字段的数目之外的任何数据字段。 对于一些实施例,源或目的地操作数中的另一个可以是通用寄存器或存储器位置。