利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.046 秒)

    Apparatus And Method To Obtain Information Regarding Suppressed Faults
    4.
    发明申请
    Apparatus And Method To Obtain Information Regarding Suppressed Faults 有权
    获取关于抑制故障信息的装置和方法

    公开(公告)号：US20140149802A1

    公开(公告)日：2014-05-29

    申请号：US13688544

    申请日：2012-11-29

    申请人： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

    发明人： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

    IPC分类号： G06F11/00

    CPC分类号： G06F11/004 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3865 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

    摘要： A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

    摘要翻译： 处理器包括执行单元，耦合到执行单元的故障掩模以及耦合到执行单元的抑制掩模。 故障掩码是存储第一多个比特值以指示多元素向量的哪些元素具有响应于在执行单元中的元素上的指令的执行而产生的相关联的故障。 抑制掩模是存储第二多个位值，以指示哪个元件将被抑制相关联的故障。 所述处理器还包括计数器逻辑，以响应于与所述第一元件相关联并从所述故障掩模接收到的第一故障的指示来增加计数器，以及与所述第一元件相关联并从所述抑制掩码接收到的第一抑制的指示。 其他实施例被描述为所要求保护的。

    METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT DETECTION FUNCTIONALITY
    5.
    发明申请
    METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT DETECTION FUNCTIONALITY 有权
    方法，装置，说明和逻辑提供矢量地址冲突检测功能

    公开(公告)号：US20140189308A1

    公开(公告)日：2014-07-03

    申请号：US13731006

    申请日：2012-12-29

    申请人： Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Brett L. Toll ,  Mark J. Charney ,  Milind B. Girkar

    发明人： Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Brett L. Toll ,  Mark J. Charney ,  Milind B. Girkar

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30021 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3887

    摘要： Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.

    摘要翻译： 指令和逻辑提供SIMD地址冲突检测功能。 一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段存储用于存储器中的数据元素的偏移量。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储可变的第二多个位以存储具有每个偏移的掩码位的冲突掩码。 响应于对向量冲突指令进行解码，执行单元将每个数据字段中的偏移量与每个较不重要的数据字段进行比较，以确定它们是否保持匹配的偏移，并且在目标寄存器中的相应冲突掩码中，设置对应于较少 具有匹配偏移的重要数据字段。 向量地址冲突检测可以与可变大小的元素一起使用，并生成冲突掩码来解决收集修改分散SIMD操作中的依赖关系。

    APPARATUS AND METHOD OF IMPROVED PERMUTE INSTRUCTIONS
    7.
    发明申请
    APPARATUS AND METHOD OF IMPROVED PERMUTE INSTRUCTIONS 有权
    改进的说明书的装置和方法

    公开(公告)号：US20130290687A1

    公开(公告)日：2013-10-31

    申请号：US13976993

    申请日：2011-12-23

    申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

    发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

    摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

    摘要翻译： 描述了具有指令执行逻辑电路的装置。 指令执行逻辑电路具有输入向量元素路由电路，以对三个不同的指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素从多个 可用于输出输出向量元素的输入向量元素位置。 输出向量元素和每个输入向量元素位置是三个不同指令的三个可用位宽之一。 该装置还包括耦合到输入向量元素路由电路以屏蔽由输入向量路由选择元件电路产生的数据结构的掩蔽层电路。 掩蔽层电路被设计为以与三个可用位宽对应的三个不同的粒度级别进行掩蔽。

    PACKED DATA OPERATION MASK REGISTER ARITHMETIC COMBINATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    8.
    发明申请
    PACKED DATA OPERATION MASK REGISTER ARITHMETIC COMBINATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    包装数据操作面板寄存器算术组合处理器，方法，系统和指令

    公开(公告)号：US20130275728A1

    公开(公告)日：2013-10-17

    申请号：US13976885

    申请日：2011-12-22

    申请人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

    发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

    摘要： A method of an aspect includes receiving a packed data operation mask register arithmetic combination instruction. The packed data operation mask register arithmetic combination instruction indicates a first packed data operation mask register, indicates a second packed data operation mask register, and indicates a destination storage location. An arithmetic combination of at least a portion of bits of the first packed data operation mask register and at least a corresponding portion of bits of the second packed data operation mask register is stored in the destination storage location in response to the packed data operation mask register arithmetic combination instruction. Other methods, apparatus, systems, and instructions are disclosed.

    摘要翻译： 一种方面的方法包括接收压缩数据操作屏蔽寄存器算术组合指令。 打包数据操作屏蔽寄存器算术组合指令指示第一打包数据操作屏蔽寄存器，指示第二打包数据操作屏蔽寄存器，并指示目的地存储位置。 响应于打包数据操作屏蔽寄存器，将第一打包数据操作屏蔽寄存器的位的至少一部分与第二打包数据操作屏蔽寄存器的位的至少相应部分的算术组合存储在目的地存储位置中 算术组合指令。 公开了其它方法，装置，系统和指令。

    Apparatus and method of improved extract instructions
    10.
    发明授权
    Apparatus and method of improved extract instructions 有权
    改进提取指令的装置和方法

    公开(公告)号：US09588764B2

    公开(公告)日：2017-03-07

    申请号：US13976998

    申请日：2011-12-23

    申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

    发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30149 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30145

    摘要： An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second instructions select a first group of input vector elements from one of multiple first non-overlapping sections of respective first and second input vectors. Each of the multiple first non-overlapping sections have a same bit width as the first group. Both the third and fourth instructions select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of multiple second non overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups at a first granularity and second granularity.

    摘要翻译： 描述了一种装置，其包括执行第一，第二，第三和第四指令的指令执行电路，第一和第二指令从第一和第二输入向量的多个第一非重叠部分之一中选择第一组输入向量元素 。 多个第一非重叠部分中的每一个具有与第一组相同的位宽度。 第三和第四指令都从相应的第三和第四输入向量的多个第二非重叠部分之一中选择第二组输入向量元素。 第二组具有比第一位宽大的第二位宽度。 多个第二非重叠部分中的每一个具有与第二组相同的位宽度。 该装置包括掩蔽层电路，以第一粒度和第二粒度掩蔽第一和第二组。