公开(公告)号：US09658850B2

公开(公告)日：2017-05-23

申请号：US13976993

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US09619236B2

公开(公告)日：2017-04-11

申请号：US13976992

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3802

摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

公开(公告)号：US20130339678A1

公开(公告)日：2013-12-19

申请号：US13997998

申请日：2011-12-23

申请人： Mikhail Plotnikov ,  Andrey Naraikan ,  Elmoustapha Ould-Ahmed-vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal

发明人： Mikhail Plotnikov ,  Andrey Naraikan ,  Elmoustapha Ould-Ahmed-vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal

IPC分类号： G06F9/30

CPC分类号： G06F9/3013 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036

摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

摘要翻译： 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。

公开(公告)号：US09600285B2

公开(公告)日：2017-03-21

申请号：US13977239

申请日：2011-12-22

申请人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark Charney

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F13/14

CPC分类号： G06F9/3017 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F13/14

摘要： A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US20160179530A1

公开(公告)日：2016-06-23

申请号：US14582007

申请日：2014-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30018

摘要： In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

摘要翻译： 在几个实施例中，指令集架构的向量扩展包括执行饱和有符号和无符号整数加法的指令。 在一个实施例中，提供了带符号饱和的向量有符号整数加法。 在一个实施例中，提供了具有无符号饱和度的向量无符号整数加法。 在一个实施例中，带符号和无符号指令都支持打包的双字和四字整数。

公开(公告)号：US20130290687A1

公开(公告)日：2013-10-31

申请号：US13976993

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

摘要翻译： 描述了具有指令执行逻辑电路的装置。 指令执行逻辑电路具有输入向量元素路由电路，以对三个不同的指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素从多个 可用于输出输出向量元素的输入向量元素位置。 输出向量元素和每个输入向量元素位置是三个不同指令的三个可用位宽之一。 该装置还包括耦合到输入向量元素路由电路以屏蔽由输入向量路由选择元件电路产生的数据结构的掩蔽层电路。 掩蔽层电路被设计为以与三个可用位宽对应的三个不同的粒度级别进行掩蔽。

公开(公告)号：US20130275728A1

公开(公告)日：2013-10-17

申请号：US13976885

申请日：2011-12-22

申请人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

摘要： A method of an aspect includes receiving a packed data operation mask register arithmetic combination instruction. The packed data operation mask register arithmetic combination instruction indicates a first packed data operation mask register, indicates a second packed data operation mask register, and indicates a destination storage location. An arithmetic combination of at least a portion of bits of the first packed data operation mask register and at least a corresponding portion of bits of the second packed data operation mask register is stored in the destination storage location in response to the packed data operation mask register arithmetic combination instruction. Other methods, apparatus, systems, and instructions are disclosed.

摘要翻译： 一种方面的方法包括接收压缩数据操作屏蔽寄存器算术组合指令。 打包数据操作屏蔽寄存器算术组合指令指示第一打包数据操作屏蔽寄存器，指示第二打包数据操作屏蔽寄存器，并指示目的地存储位置。 响应于打包数据操作屏蔽寄存器，将第一打包数据操作屏蔽寄存器的位的至少一部分与第二打包数据操作屏蔽寄存器的位的至少相应部分的算术组合存储在目的地存储位置中 算术组合指令。 公开了其它方法，装置，系统和指令。

公开(公告)号：US09760371B2

公开(公告)日：2017-09-12

申请号：US13976885

申请日：2011-12-22

申请人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036

摘要： A method of an aspect includes receiving a packed data operation mask register arithmetic combination instruction. The packed data operation mask register arithmetic combination instruction indicates a first packed data operation mask register, indicates a second packed data operation mask register, and indicates a destination storage location. An arithmetic combination of at least a portion of bits of the first packed data operation mask register and at least a corresponding portion of bits of the second packed data operation mask register is stored in the destination storage location in response to the packed data operation mask register arithmetic combination instruction. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US20170192781A1

公开(公告)日：2017-07-06

申请号：US14984124

申请日：2015-12-30

申请人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

发明人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30192 ,  G06F9/3455

摘要： Detailed herein are systems, apparatuses, and methods for strided loads. In an embodiment, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

公开(公告)号：US09588764B2

公开(公告)日：2017-03-07

申请号：US13976998

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30145

摘要： An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second instructions select a first group of input vector elements from one of multiple first non-overlapping sections of respective first and second input vectors. Each of the multiple first non-overlapping sections have a same bit width as the first group. Both the third and fourth instructions select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of multiple second non overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups at a first granularity and second granularity.

摘要翻译： 描述了一种装置，其包括执行第一，第二，第三和第四指令的指令执行电路，第一和第二指令从第一和第二输入向量的多个第一非重叠部分之一中选择第一组输入向量元素 。 多个第一非重叠部分中的每一个具有与第一组相同的位宽度。 第三和第四指令都从相应的第三和第四输入向量的多个第二非重叠部分之一中选择第二组输入向量元素。 第二组具有比第一位宽大的第二位宽度。 多个第二非重叠部分中的每一个具有与第二组相同的位宽度。 该装置包括掩蔽层电路，以第一粒度和第二粒度掩蔽第一和第二组。