公开(公告)号：US20110075475A1

公开(公告)日：2011-03-31

申请号：US12965126

申请日：2010-12-10

Applicant: MING-HSIU LEE

Inventor： MING-HSIU LEE

IPC: G11C11/21

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

公开(公告)号：US20090175071A1

公开(公告)日：2009-07-09

申请号：US11970348

申请日：2008-01-07

Applicant: MING-HSIU LEE ,  Bipin Rajendran ,  Chung Hon Lam

Inventor： MING-HSIU LEE ,  Bipin Rajendran ,  Chung Hon Lam

IPC: G11C11/00 ,  G11C29/00 ,  G01R31/28

CPC classification number: G11C29/50 ,  G11C13/0004 ,  G11C29/50008 ,  Y10T29/49004

Abstract: A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.

Abstract translation: 用于测试集成电路存储器件的方法包括将测试脉冲序列应用于器件上的存储器单元，其中测试脉冲导致具有取决于测试脉冲的幅度的存储器单元的电流。 响应于测试脉冲的顺序测量存储器单元中的电阻。 从电阻测量中提取参数集，其包括至少一个数值系数，其模拟所测量的电阻对通过存储器单元的电流的振幅的依赖性。 提取的数值系数或系数与存储器件相关联，并用于控制制造操作。