公开(公告)号：US09070860B2

公开(公告)日：2015-06-30

申请号：US13601209

申请日：2012-08-31

Applicant: Wei-Chih Chien ,  Ming-Hsiu Lee

Inventor： Wei-Chih Chien ,  Ming-Hsiu Lee

IPC: H01L45/00 ,  G11C13/00 ,  G11C29/50

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2213/72 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/146

Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

Abstract translation: 提供了一种电阻记忆单元，包括第一电极，钨金属层，金属氧化物层和第二电极。 钨金属层设置在第一电极上。 金属氧化物层设置在钨金属层上。 第二电极包括第一连接焊盘，第二连接焊盘和电连接在第一连接焊盘和第二连接焊盘之间的桥接部分。 桥接部分设置在金属氧化物层上或围绕金属氧化物层。 电阻存储单元通过穿过金属氧化物层和钨金属层的第一电流路径或从第一连接焊盘延伸到第二连接焊盘的第二电流路径来调节金属氧化物层的电阻率。

公开(公告)号：US20140131653A1

公开(公告)日：2014-05-15

申请号：US13675923

申请日：2012-11-13

Applicant: FENG-MING LEE ,  YU-YU LIN ,  MING-HSIU LEE

Inventor： FENG-MING LEE ,  YU-YU LIN ,  MING-HSIU LEE

IPC: H01L45/00 ,  G11C11/00

CPC classification number: G11C11/00 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract translation: 可编程金属化器件包括在第一和第二电极之间串联的第一电极和第二电极以及电介质层，导电离子阻挡层和离子供给层。 在操作中，在电介质层中形成或破坏导电桥，以使用具有相同极性的偏置电压来表示数据值，从而能够使用二极管接入装置。 为了形成导电桥，施加足够高的偏压，使得离子将导电离子阻挡层穿透到电介质层中，然后形成细丝或桥。 为了破坏导电桥，施加相同极性的偏压，导致电流流过结构，同时离子流被导电离子阻挡层阻挡。 作为焦耳加热的结果，介电层中的任何桥分解。

公开(公告)号：US08699258B2

公开(公告)日：2014-04-15

申请号：US13212493

申请日：2011-08-18

Applicant: Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

Inventor： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

IPC: G11C11/00

CPC classification number: G11C7/1045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

Abstract translation: 描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。 本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。 在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。

公开(公告)号：US20130094273A1

公开(公告)日：2013-04-18

申请号：US13706001

申请日：2012-12-05

Applicant: WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

Inventor： WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/249 ,  H01L28/24 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

Abstract translation: 3D存储器件基于导电柱阵列和多个图案化的导体平面，其包括在左侧和右侧界面区域处邻近导电柱的左侧和右侧导体。 左侧和右侧界面区域中的存储元件包括可以通过内置自切换行为表征的可编程过渡金属氧化物或其它可编程电阻材料。 可以使用二维解码来选择导电柱，并且可以使用与左侧和右侧选择相结合的第三维度上的解码来选择多个平面中的左侧和右侧导体。

公开(公告)号：US20120231613A1

公开(公告)日：2012-09-13

申请号：US13476964

申请日：2012-05-21

Applicant: HSIANG-LAN LUNG ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING HSIU LEE ,  HANG-TING LUE

Inventor： HSIANG-LAN LUNG ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING HSIU LEE ,  HANG-TING LUE

IPC: H01L21/20

CPC classification number: G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract translation: 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US20120188813A1

公开(公告)日：2012-07-26

申请号：US13212493

申请日：2011-08-18

Applicant: Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

Inventor： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Yan-Ru Chen

IPC: G11C11/21

CPC classification number: G11C7/1045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

Abstract translation: 描述了用于操作这种装置的存储器件和方法，其可以有效地将阵列中的金属氧化物存储元件编程，同时还避免施加不必要的高电压脉冲。 本文描述的编程操作包括在金属氧化物存储元件上施加较低电压脉冲以建立期望的电阻状态，并且仅当较低电压脉冲不足以对存储元件进行编程时才施加较高电压脉冲。 在这样做时，可以避免与在存储元件上施加不必要的高电压有关的问题。

公开(公告)号：US08178407B2

公开(公告)日：2012-05-15

申请号：US12561395

申请日：2009-09-17

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Chao-I Wu ,  Ming-Chang Kuo

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0475 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract translation: 包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。 因此，可以实现非常紧凑，高密度的存储器阵列。 存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。 可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

公开(公告)号：US20100314601A1

公开(公告)日：2010-12-16

申请号：US12484955

申请日：2009-06-15

Applicant: MING-HSIU LEE

Inventor： MING-HSIU LEE

IPC: H01L45/00 ,  H01L21/06

CPC classification number: H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.

Abstract translation: 具有在有源区域中具有改变的化学计量的相变材料元件的存储器件在设定状态电阻中不会出现漂移。 一种用于制造存储器件的方法包括：首先制造集成电路，该集成电路包括具有大体积化学计量的相变材料体的相变存储器单元的阵列; 然后将成形电流施加到阵列中的相变存储器单元，以将相变材料的主体的有源区域中的主体化学计量改变为改变的化学计量，而不会干扰有源区域外的主体化学计量。 主要化学计量学的特征在于在有源区域外的热力学条件下的稳定性，而改性的化学计量学的特征在于活性区域内的热力学条件下的稳定性。

公开(公告)号：US20100295009A1

公开(公告)日：2010-11-25

申请号：US12471287

申请日：2009-05-22

Applicant: Hsiang-Lan Lung ,  Chung H. Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

Inventor： Hsiang-Lan Lung ,  Chung H. Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

Abstract translation: 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

公开(公告)号：US07817472B2

公开(公告)日：2010-10-19

申请号：US12169155

申请日：2008-07-08

Applicant: Ming-Chang Kuo ,  Ming-Hsiu Lee ,  Chao-I Wu

Inventor： Ming-Chang Kuo ,  Ming-Hsiu Lee ,  Chao-I Wu

IPC: G11C16/04

CPC classification number: G11C16/0416 ,  G11C16/10 ,  G11C16/14

Abstract: An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array.

Abstract translation: 提供了一种存储器阵列的操作方法。 操作方法包括执行编程操作。 通过将第一电压施加到存储器阵列的位线并将第二电压施加到存储器阵列的多个字线来执行编程操作，以同时对存储器阵列中的多个选择的存储器单元进行编程。