公开(公告)号：US20020186063A1

公开(公告)日：2002-12-12

申请号：US10196479

申请日：2002-07-17

Applicant: GCT Semiconductor, Inc.

Inventor： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC: H03L007/06

CPC classification number: H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

Abstract: A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

Abstract translation: 提供了一种锁相环（PLL）及其使用方法，包括多反馈CMOS压控振荡器（VCO）和多相采样分数N预分频器。 PLL为单芯片CMOS射频（RF）通信系统提供了更高的性能特性。 多反馈CMOS VCO在降低VCO信号的上升/下降时间的同时保持VCO信号的幅度。 多反馈CMOS VCO进一步降低了电源噪声影响。 多相采样分数N预分频器为CMOS VCO提供足够的带宽，同时保持光谱纯度并减少分数。 多相采样分数N预分频器可以包括分频器，采样器电路，选择器电路和模块化计数器。

公开(公告)号：US20020030529A1

公开(公告)日：2002-03-14

申请号：US09985897

申请日：2001-11-06

Applicant: GCT Semiconductor, Inc.

Inventor： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC: G06G007/16

CPC classification number: H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

Abstract: A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

Abstract translation: 根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。 多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。 开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。 耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。 输入电路包括接收输入信号的晶体管。 第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。 优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。 混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。