公开(公告)号：US09728456B2

公开(公告)日：2017-08-08

申请号：US15420467

申请日：2017-01-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, Jr.

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

公开(公告)号：US20170170070A1

公开(公告)日：2017-06-15

申请号：US15443523

申请日：2017-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09627257B2

公开(公告)日：2017-04-18

申请号：US15175835

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L29/66 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170047254A1

公开(公告)日：2017-02-16

申请号：US15175835

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L27/11 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170047252A1

公开(公告)日：2017-02-16

申请号：US15175776

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。

公开(公告)号：US20160379932A1

公开(公告)日：2016-12-29

申请号：US14753407

申请日：2015-06-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Sukwon Hong ,  William J. Taylor, JR.

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

Abstract translation: 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

公开(公告)号：US09397049B1

公开(公告)日：2016-07-19

申请号：US14822654

申请日：2015-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L27/11 ,  H01L21/027

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。

公开(公告)号：US20180374932A1

公开(公告)日：2018-12-27

申请号：US16120870

申请日：2018-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/311 ,  H01L27/11 ,  H01L21/027

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

公开(公告)号：US09899259B2

公开(公告)日：2018-02-20

申请号：US15443523

申请日：2017-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/027 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170278753A1

公开(公告)日：2017-09-28

申请号：US15618880

申请日：2017-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L27/11 ,  H01L29/66 ,  H01L23/535 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.