公开(公告)号：US20190019915A1

公开(公告)日：2019-01-17

申请号：US15650427

申请日：2017-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srinivasa BANNA ,  Deepak NAYAK ,  Luke ENGLAND ,  Rahul AGARWAL

IPC: H01L31/18 ,  H01L27/15

Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

公开(公告)号：US20160293579A1

公开(公告)日：2016-10-06

申请号：US14678016

申请日：2015-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke ENGLAND ,  Sukeshwar KANNAN ,  Daniel SMITH

IPC: H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: Through-silicon-vias (TSV) to back end of line (BEOL) integration structures and a method of manufacturing the same are disclosed. Embodiments include providing a bottom die of a three-dimensional (3D) integrated circuit (IC) stack, the bottom die having a connection pad; providing a top die of the 3D IC stack, the top die including a plurality of metallization layers having a plurality of intermetal vias provided between the plurality of metallization layers; forming a BEOL connection structure between the bottom and top dies, the BEOL connection structure having a plurality of power supply TSVs; and connecting the connection pad electrically to the intermetal vias through the power supply TSVs.

Abstract translation: 披露了贯穿硅通孔（TSV）到后端（BEOL）集成结构及其制造方法。 实施例包括提供三维（3D）集成电路（IC）堆叠的底模，所述底模具有连接垫; 提供3D IC堆叠的顶模，所述顶模具包括多个金属化层，所述多个金属化层具有设置在所述多个金属化层之间的多个金属间通路; 在底部和顶部模具之间形成BEOL连接结构，BEOL连接结构具有多个电源TSV; 并通过电源TSV将连接垫电连接到金属间通孔。