公开(公告)号：US20150171001A1

公开(公告)日：2015-06-18

申请号：US14106340

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Daniel SMITH ,  Kumarapuram GOPALAKRISHNAN ,  Hung-Wei LIU

IPC: H01L23/498 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033

CPC classification number: H01L21/32051 ,  H01L21/3081 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with a protection layer for a dielectric mask layer are provided. One method includes, for instance; obtaining a substrate having at least one of a dielectric layer and a metal layer; forming a first SiCN dielectric mask layer on a top surface of at least one of the dielectric layer and a metal layer; and forming a silicon nitride (SiNx) cap layer on a top surface of the first SiCN dielectric mask layer. One intermediate semiconductor device includes, for instance: a substrate having at least one of a dielectric layer and a metal layer; a first SiCN dielectric mask layer on a top surface of at least one of the dielectric layer and a metal layer; and a silicon nitride (SiNx) cap layer on a top surface of the first SiCN dielectric mask layer.

Abstract translation: 提供了用于形成具有用于介电掩模层的保护层的半导体器件的器件和方法。 一种方法包括： 获得具有电介质层和金属层中的至少一个的衬底; 在所述电介质层和金属层中的至少一个的顶表面上形成第一SiCN电介质掩模层; 以及在所述第一SiCN介电掩模层的顶表面上形成氮化硅（SiNx）覆盖层。 一个中间半导体器件包括例如：具有电介质层和金属层中的至少一个的衬底; 在所述电介质层和金属层中的至少一个的顶表面上的第一SiCN介电掩模层; 和在第一SiCN介电掩模层的顶表面上的氮化硅（SiNx）覆盖层。

公开(公告)号：US20160293579A1

公开(公告)日：2016-10-06

申请号：US14678016

申请日：2015-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke ENGLAND ,  Sukeshwar KANNAN ,  Daniel SMITH

IPC: H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: Through-silicon-vias (TSV) to back end of line (BEOL) integration structures and a method of manufacturing the same are disclosed. Embodiments include providing a bottom die of a three-dimensional (3D) integrated circuit (IC) stack, the bottom die having a connection pad; providing a top die of the 3D IC stack, the top die including a plurality of metallization layers having a plurality of intermetal vias provided between the plurality of metallization layers; forming a BEOL connection structure between the bottom and top dies, the BEOL connection structure having a plurality of power supply TSVs; and connecting the connection pad electrically to the intermetal vias through the power supply TSVs.

Abstract translation: 披露了贯穿硅通孔（TSV）到后端（BEOL）集成结构及其制造方法。 实施例包括提供三维（3D）集成电路（IC）堆叠的底模，所述底模具有连接垫; 提供3D IC堆叠的顶模，所述顶模具包括多个金属化层，所述多个金属化层具有设置在所述多个金属化层之间的多个金属间通路; 在底部和顶部模具之间形成BEOL连接结构，BEOL连接结构具有多个电源TSV; 并通过电源TSV将连接垫电连接到金属间通孔。