公开(公告)号：US09543215B2

公开(公告)日：2017-01-10

申请号：US14691233

申请日：2015-04-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

IPC: H01L21/8238 ,  H01L29/167 ,  H01L21/324 ,  H01L29/10 ,  H01L21/308 ,  H01L21/225

CPC classification number: H01L21/823821 ,  H01L21/2253 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

Abstract translation: 减少由于短路效应引起的三维半导体器件漏电的方法包括提供起始半导体结构，该结构包括具有n型器件区域和p型器件区域的半导体衬底，p型 器件区域，其包括p型半导体材料的上层，两个区域上的硬掩模层，以及用于在每个区域中构图至少一个翅片的结构上的掩模。 该方法还包括在起始半导体结构的每个区域中形成部分散热片，在该结构上形成共形衬垫，在每个区域中产生穿通停止（PTS），使得每个PTS扩散穿过顶部 并且从部分翅片在每个区域中产生全鳍。

公开(公告)号：US20150137308A1

公开(公告)日：2015-05-21

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.