公开(公告)号：US10468481B2

公开(公告)日：2019-11-05

申请号：US15875132

申请日：2018-01-19

申请人： GLOBALFOUNDRIES INC.

发明人： Haiting Wang ,  Hui Zang ,  Chun Yu Wong ,  Kwan-Yong Lim

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L27/088

摘要： A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US09960086B2

公开(公告)日：2018-05-01

申请号：US15274974

申请日：2016-09-23

申请人： GLOBALFOUNDRIES INC.

发明人： Mira Park ,  Kwan-Yong Lim ,  Steven Bentley ,  Amitabh Jain

IPC分类号： H01L21/31 ,  H01L21/82 ,  H01L21/30 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/223 ,  H01L21/324

CPC分类号： H01L21/823892 ,  H01L21/2236 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/785

摘要： At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

公开(公告)号：US09911738B1

公开(公告)日：2018-03-06

申请号：US15586621

申请日：2017-05-04

申请人： GLOBALFOUNDRIES Inc.

发明人： Hiroaki Niimi ,  Kwan-Yong Lim ,  Brent A. Anderson ,  Junli Wang

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376 ,  H01L29/7827

摘要： Methods for forming a structure that includes vertical-transport field-effect transistors and structures that include vertical-transport field-effect transistors. A first semiconductor fin is separated from a second semiconductor fin by a gap. A gate stack is conformally deposited that extends across the first semiconductor fin, the second semiconductor fin, and the gap. A section of the gate stack is located in the gap. A gate strap layer is formed in the gap on the section of the gate stack. The gate stack is patterned to form a first gate electrode associated with the first semiconductor fin and a second gate electrode associated with the second semiconductor fin. The gate strap layer masks the section of the gate stack when the gate stack is patterned. The first gate electrode is connected with the second gate electrode by the gate strap layer and the section of the gate stack.

公开(公告)号：US20180061832A1

公开(公告)日：2018-03-01

申请号：US15801023

申请日：2017-11-01

申请人： GLOBALFOUNDRIES INC.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US09543215B2

公开(公告)日：2017-01-10

申请号：US14691233

申请日：2015-04-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

IPC分类号： H01L21/8238 ,  H01L29/167 ,  H01L21/324 ,  H01L29/10 ,  H01L21/308 ,  H01L21/225

CPC分类号： H01L21/823821 ,  H01L21/2253 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

摘要： A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

摘要翻译： 减少由于短路效应引起的三维半导体器件漏电的方法包括提供起始半导体结构，该结构包括具有n型器件区域和p型器件区域的半导体衬底，p型 器件区域，其包括p型半导体材料的上层，两个区域上的硬掩模层，以及用于在每个区域中构图至少一个翅片的结构上的掩模。 该方法还包括在起始半导体结构的每个区域中形成部分散热片，在该结构上形成共形衬垫，在每个区域中产生穿通停止（PTS），使得每个PTS扩散穿过顶部 并且从部分翅片在每个区域中产生全鳍。

公开(公告)号：US09263446B1

公开(公告)日：2016-02-16

申请号：US14511286

申请日：2014-10-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Chanro Park

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28

CPC分类号： H01L27/0922 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： One illustrative method disclosed herein includes, among other things, forming a shared gate cavity that spans across an isolation region and is positioned above first and second active regions, forming at least one layer of material in the shared gate cavity above the first and second active regions and above the isolation region, forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region, with the first masking layer in position, performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region, and removing the first masking layer.

摘要翻译： 本文公开的一种说明性方法尤其包括形成跨越隔离区并且位于第一和第二有源区上方的共享栅极腔，在第一和第二有源区上方的共享栅极腔中形成至少一层材料 区域并且在隔离区域上方，形成第一掩模层，其覆盖位于第一和第二有源区域上方的共享栅极腔的部分，同时暴露位于隔离区域上方的共享栅极腔的一部分，其中第一掩模层位于 执行至少一个第一蚀刻工艺以去除所述隔离区域上方的所述共享栅腔的所述暴露部分中的所述至少一层材料的至少一部分，以及去除所述第一掩模层。

公开(公告)号：US09236308B1

公开(公告)日：2016-01-12

申请号：US14463013

申请日：2014-08-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

IPC分类号： H01L21/8242 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/31116 ,  H01L27/0886 ,  H01L29/66818

摘要： Methods of fabricating fin structures having exposed upper fin portions with a uniform exposure height are disclosed herein. The fabrication methods include providing a substrate with plurality of fins and a dielectric material disposed between and over the plurality of fins, planarizing the dielectric material and the plurality of fins, and uniformly recessing the dielectric material to a pre-selected depth below upper surfaces of the plurality of fins to expose upper fin portions. The exposed upper fin portions, as a result of uniformly recessing the dielectric material, have a uniform exposure height above the recessed dielectric material. A protective film may be provided over the recessed dielectric material and exposed upper fin portions to preserve the uniform exposure height of the upper fin portions. The uniform exposure height of the exposed upper fin portions facilitates subsequent formation of one or more circuit structures above the substrate.

摘要翻译： 本文公开了制造具有暴露的具有均匀曝光高度的上翅片部分的翅片结构的方法。 制造方法包括提供具有多个翅片的基板和设置在多个翅片之间和之上的介电材料，平坦化介电材料和多个翅片，并均匀地将电介质材料凹陷到下表面下方的预选深度 多个翅片以暴露上部翅片部分。 暴露的上部翅片部分，由于均匀地凹陷介电材料，在凹入的电介质材料上方具有均匀的曝光高度。 可以在凹陷的电介质材料和暴露的上部翅片部分上设置保护膜，以保持上部翅片部分的均匀的曝光高度。 暴露的上部翅片部分的均匀曝光高度有助于随后在基底上方形成一个或多个电路结构。

公开(公告)号：US10529724B2

公开(公告)日：2020-01-07

申请号：US16056660

申请日：2018-08-07

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Manfred Eller ,  Kwan-Yong Lim

IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

摘要： A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

公开(公告)号：US20190267387A1

公开(公告)日：2019-08-29

申请号：US15903203

申请日：2018-02-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim

IPC分类号： H01L27/11 ,  G11C8/14 ,  H01L23/522 ,  H01L23/50 ,  H01L27/105 ,  H01L21/48 ,  H01L21/768

摘要： A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.

公开(公告)号：US20180323269A1

公开(公告)日：2018-11-08

申请号：US15585865

申请日：2017-05-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material