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    ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING
    14.
    发明申请
    ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING 有权
    高性能，高能效，可编程图像处理的架构

    公开(公告)号：US20160314555A1

    公开(公告)日：2016-10-27

    申请号：US14694828

    申请日：2015-04-23

    Applicant: Google Inc.

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Albert Meixner ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  David Patterson ,  Neeti Desai ,  Donald Stark ,  Edward T. Chang ,  William R. Mark

    IPC: G06T1/20 ,  G06T1/60 ,  H04N5/91 ,  H04N5/378

    CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N5/378 ,  H04N5/91

    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

    Abstract translation: 描述了一种装置。 该装置包括图像处理单元。 图像处理单元包括网络。 图像处理单元包括多个模板处理器电路，每个模板处理器电路各自包括耦合到二维移位寄存器阵列结构的执行单元通道的阵列，以通过执行程序代码来同时处理多个重叠模版。 图像处理单元包括分别耦合在多个模板处理器和网络之间的多个片材生成器。 片材生成器将图像数据的输入线组分解成图像数据的输入片以供模板处理器处理，并且从从模版处理器接收的图像数据的输出片材中形成图像数据的输出线组。 图像处理单元包括耦合到网络的多个行缓冲单元，以在从生成模板处理器到消耗模板处理器的方向上传递线组，以实现整个程序流程。

    Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure
    15.
    发明申请
    Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure 审中-公开
    虚拟图像处理器指令集架构（ISA）和具有二维移位阵列结构的存储器模型和示例性目标硬件

    公开(公告)号：US20160313980A1

    公开(公告)日：2016-10-27

    申请号：US14694890

    申请日：2015-04-23

    Applicant: Google Inc.

    Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

    IPC: G06F9/44 ,  G06F9/30

    CPC classification number: G06F17/5009 ,  G06F8/10 ,  G06F8/20 ,  G06F9/3004 ,  G06F9/30101 ,  G06T1/20 ,  G06T2200/28

    Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

    Abstract translation: 描述了一种方法，其包括在应用软件开发环境内实例化具有预期存储器的第一和第二区域的指令集架构和存储器模型的虚拟处理器。 第一个保留区域是保留输入图像数组的数据。 第二保留区域是保留输出图像数组的数据。 该方法还包括通过自动地针对第一保留区域来模拟指令集架构的存储器加载指令的执行，并且相对于虚拟处理器在正交坐标系中的位置识别具有第一和第二坐标的期望输入数据并以指令格式表示 的存储器加载指令。

    Multi-functional execution lane for image processor
    16.
    发明授权
    Multi-functional execution lane for image processor 有权

    公开(公告)号：US09830150B2

    公开(公告)日：2017-11-28

    申请号：US14960334

    申请日：2015-12-04

    Applicant: Google Inc.

    Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

    IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

    CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/80

    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

    COMPILER MANAGED MEMORY FOR IMAGE PROCESSOR
    17.
    发明申请
    COMPILER MANAGED MEMORY FOR IMAGE PROCESSOR 审中-公开

    公开(公告)号：US20170287105A1

    公开(公告)日：2017-10-05

    申请号：US15625972

    申请日：2017-06-16

    Applicant: Google Inc.

    Inventor： Albert Meixner ,  Hyunchul Park ,  Qiuling Zhu ,  Jason Rupert Redgrave

    IPC: G06T1/60 ,  G06T1/20

    CPC classification number: G06T1/60 ,  G06F9/3887 ,  G06T1/20

    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.

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