公开(公告)号：US5168501A

公开(公告)日：1992-12-01

申请号：US475637

申请日：1990-02-06

申请人： Peter B. Criswell

发明人： Peter B. Criswell

IPC分类号： G01R31/3185 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273 ,  G06F11/32 ,  G11C29/00

CPC分类号： G01R31/318544 ,  G06F11/322 ,  G06F11/327 ,  G06F11/22 ,  G06F11/27 ,  G06F11/2736 ,  G11C29/74

摘要： The present invention method is of the type which may be implemented in existing maintenance controllers of large mainframe computers and comprises a method for checking hardware errors which exists in the computing system and are displayable on a display of the type employed to display the state of scan settable latches. The novel method permits a more compact display of the functional operation of the computing system thus permitting a customer engineer to easily identify a faulty latch copy based solely on employing the method and prescribed format. The novel method includes assimilating the state of scannable logic devices such as latches and designators in the computer system and defining functionally the system in which they are located. The binary state of the individual latches are then subdivided into a plurality of one or more groups having the same number of copies and are assigned to a duplicate pseudo having four unique features which define each of the latches in a group. Each of the plurality of groups of latches are converted from their binary form to a code or code group which compacts the binary information and permits deviations of latches within the groups to be more easily detected. Means are provided for detecting errors within groups and for detecting the latch within the group in which the error occurs and for listing the duplicate latches that have failed with associated information which identifies their location.

摘要翻译： 本发明的方法是可以在大型主机计算机的现有维护控制器中实现的，并且包括用于检查计算系统中存在的硬件错误的方法，并且可以在用于显示扫描状态的类型的显示器上显示 可设置的锁存器。 该新颖的方法允许更紧凑地显示计算系统的功能操作，从而允许客户工程师基于采用该方法和规定的格式容易地识别错误的锁存器副本。 新颖的方法包括在计算机系统中同化诸如锁存器和指示符之类的可扫描逻辑器件的状态并且功能地定义它们所在的系统。 各个锁存器的二进制状态然后被细分为具有相同拷贝数的多个一个或多个组，并被分配给具有限定组中的每个锁存器的四个唯一特征的重复伪。 多个锁存器组中的每一个从其二进制形式转换成代码或代码组，该代码或代码组压缩二进制信息并允许组内的锁存器的偏差更容易被检测。 提供了用于检测组内的错误并检测发生错误的组内的锁存器并且用于列出具有标识其位置的关联信息失败的重复锁存器的装置。

公开(公告)号：US5081629A

公开(公告)日：1992-01-14

申请号：US641626

申请日：1991-01-16

申请人： Peter B. Criswell ,  Michael J. Stella

发明人： Peter B. Criswell ,  Michael J. Stella

IPC分类号： G06F1/04 ,  G06F11/10 ,  G06F11/16

CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F11/104 ,  G06F11/1608

摘要： A clock error detection system is provided for a data processing system that employs multiphase clock signals and dual, substantially identical electronic modules. The clock error detection system employs one clock error detection circuit on one module and a second clock error detection circuit on the other electronic module. An error collector is coupled to the first and second clock error detection circuits on both modules to receive the fault signals. Two complementary residue code generators with different moduli are used in each electronic module to generate clock phase error detection signals, which may be used to detect either missing or extra clock phases.

摘要翻译： 为采用多相时钟信号和双重基本相同的电子模块的数据处理系统提供时钟误差检测系统。 时钟误差检测系统在一个模块上使用一个时钟误差检测电路，在另​​一个电子模块上采用第二个时钟误差检测电路。 误差采集器耦合到两个模块上的第一和第二时钟误差检测电路以接收故障信号。 在每个电子模块中使用两个具有不同模量的互补残留码发生器来产生时钟相位误差检测信号，其可用于检测丢失或额外的时钟相位。

公开(公告)号：US07831807B1

公开(公告)日：2010-11-09

申请号：US10176841

申请日：2002-06-20

申请人： David C. Johnson ,  Peter B. Criswell

发明人： David C. Johnson ,  Peter B. Criswell

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/328

摘要： A system and method for modifying the hardware instruction set of an instruction processor is disclosed. The invention utilizes one or more bits of an instruction opcode and one or more programmable bits stored within the instruction processor to generate a branch address. The branch address is then used to address a storage device such as a microcode RAM to retrieve one or more microcode instructions that control execution of the instruction opcode. Address generation is controlled by selecting a previously unused instruction opcode, then modifying the programmable bits as necessary to generate a desired branch address. By loading modified microcode instructions at the branch address, instruction execution can be modified without changing the hardware design.

摘要翻译： 公开了一种用于修改指令处理器的硬件指令集的系统和方法。 本发明利用指令操作码的一个或多个位以及存储在指令处理器内的一个或多个可编程位来产生分支地址。 然后，分支地址用于寻址诸如微代码RAM的存储设备，以检索控制指令操作码执行的一个或多个微代码指令。 通过选择先前未使用的指令操作码来控制地址生成，然后根据需要修改可编程位以产生所需的分支地址。 通过在分支地址上加载修改的微代码指令，可以修改指令执行而不改变硬件设计。

公开(公告)号：US5931940A

公开(公告)日：1999-08-03

申请号：US786924

申请日：1997-01-23

申请人： Richard Shelton ,  Peter B. Criswell

发明人： Richard Shelton ,  Peter B. Criswell

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/312 ,  G06F9/32 ,  G06F9/355 ,  G06F13/00

CPC分类号： G06F9/30018 ,  G06F9/30021 ,  G06F9/30043 ,  G06F9/30069 ,  G06F9/355

摘要： Apparatus and a method for providing a single instruction that can load a character from memory and perform a character compare. In an illustrative embodiment, this is accomplished by providing indexing apparatus which permits indexing on character boundaries. The characters are loaded from memory, and provided to an ALU unit in a processor, wherein a compare is made with a desired value. The ALU provides a compare result to a jump skip logic block, which notifies the processor whether the instruction immediately following the instruction of the present invention should be skipped or executed.

摘要翻译： 用于提供可以从存储器加载字符并执行字符比较的单个指令的装置和方法。 在说明性实施例中，这是通过提供允许在字符边界上进行索引的索引装置来实现的。 字符从存储器加载并提供给处理器中的ALU单元，其中以期望值进行比较。 ALU向跳过跳过逻辑块提供比较结果，该逻辑块通知处理器是否应该跳过或执行紧跟在本发明的指令之后的指令。

公开(公告)号：US5819072A

公开(公告)日：1998-10-06

申请号：US671432

申请日：1996-06-27

申请人： Louis B. Bushard ,  Peter B. Criswell ,  Douglas A. Fuller ,  James E. Rezek ,  Richard F. Paul

发明人： Louis B. Bushard ,  Peter B. Criswell ,  Douglas A. Fuller ,  James E. Rezek ,  Richard F. Paul

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.

摘要翻译： 对于对于多个并行路径具有不同时序约束的电路设计执行关键路径时序分析的方法。 方法包括清除电路设计的状态，将电路设计中的控制线设置为所选择的一组控制信号，以及通过使用所选择的一组控制来模拟电路设计来识别要标记的时序分析的电路设计的阻塞网 信号作为输入信号。 识别的阻塞点被添加到标识要分析的电路设计中的路径的列表。 处理所有可能的控制信号组。 然后使用列表作为输入数据对电路设计进行时序分析。 关键的一步是识别阻塞点。 针对具有未知值的电路设计中的栅极的每个净输入识别阻塞点，以及针对所选择的一组控制信号的来自栅极的输出网上的已知值。 输入到定时分析工具的阻塞点确保在关键路径时序分析期间对这些网络进行分析，因此检测到电路设计中的所有可能的定时违规。