公开(公告)号：US20170249717A1

公开(公告)日：2017-08-31

申请号：US15427374

申请日：2017-02-08

Applicant: Google Inc.

Inventor： Albert MEIXNER ,  Hyunchul PARK ,  Qiuling ZHU ,  Jason Rupert REDGRAVE

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/3887 ,  G06T1/20

Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array. The method also includes repeatedly moving a next sheet of image data to be fully loaded into the two dimensional shift register array from a second location of the memory to the first location of the memory.

公开(公告)号：US20180330465A1

公开(公告)日：2018-11-15

申请号：US15595242

申请日：2017-05-15

Applicant: Google Inc.

Inventor： Jason REDGRAVE ,  Albert MEIXNER ,  Qiuling ZHU ,  Ji KIM ,  Artem VASILYEV ,  Ofer SHACHAM

IPC: G06T1/20 ,  G06F12/0813 ,  H04L25/40 ,  G06F15/80

CPC classification number: G06T1/20 ,  G06F12/0813 ,  G06F15/8023 ,  H04L25/40

Abstract: A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.

公开(公告)号：US20180329746A1

公开(公告)日：2018-11-15

申请号：US15594529

申请日：2017-05-12

Applicant: Google Inc.

Inventor： Hyunchul PARK ,  Albert MEIXNER

IPC: G06F9/50 ,  G06T1/20

Abstract: A method is described. The method includes calculating data transfer metrics for kernel-to-kernel connections of a program having a plurality of kernels that is to execute on an image processor. The image processor includes a plurality of processing cores and a network connecting the plurality of processing cores. Each of the kernel-to-kernel connections include a producing kernel that is to execute on one of the processing cores and a consuming kernel that is to execute on another one of the processing cores. The consuming kernel is to operate on data generated by the producing kernel. The method also includes assigning kernels of the plurality of kernels to respective ones of the processing cores based on the calculated data transfer metrics.

公开(公告)号：US20180329479A1

公开(公告)日：2018-11-15

申请号：US15595600

申请日：2017-05-15

Applicant: Google Inc.

Inventor： Albert MEIXNER

IPC: G06F3/00 ,  G11C19/38 ,  G06T7/73 ,  H04N19/44

CPC classification number: G06F3/007 ,  G06T1/20 ,  G06T7/73 ,  G11C19/38 ,  H04N19/44

Abstract: An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.

公开(公告)号：US20180005059A1

公开(公告)日：2018-01-04

申请号：US15201134

申请日：2016-07-01

Applicant: Google Inc.

Inventor： Edward CHANG ,  Daniel Frederic FINCHELSTEIN ,  Szepo Robert HUNG ,  Albert MEIXNER ,  Ofer SHACHAM

IPC: G06K9/00 ,  G11C19/00

CPC classification number: G06K9/00986 ,  G06T1/20 ,  G11C19/00

Abstract: A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence that includes: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing mathematical operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence that includes: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined at least in part from the mathematical operations of the first sequence. The second sequence further includes performing mathematical operations on items of content from the set of first locations and respective items of content from the set of second locations with the execution lane array.