公开(公告)号：US20180329479A1

公开(公告)日：2018-11-15

申请号：US15595600

申请日：2017-05-15

申请人： Google Inc.

发明人： Albert MEIXNER

IPC分类号： G06F3/00 ,  G11C19/38 ,  G06T7/73 ,  H04N19/44

CPC分类号： G06F3/007 ,  G06T1/20 ,  G06T7/73 ,  G11C19/38 ,  H04N19/44

摘要： An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.

公开(公告)号：US10002559B2

公开(公告)日：2018-06-19

申请号：US15654325

申请日：2017-07-19

申请人： NEC DISPLAY SOLUTIONS, LTD.

发明人： Nozomu Kano

IPC分类号： G09G3/20 ,  G06F3/042 ,  G06F3/0484 ,  G09G3/00 ,  G06F3/00

CPC分类号： G09G3/2092 ,  G06F3/007 ,  G06F3/0425 ,  G06F3/0484 ,  G06F3/1446 ,  G09G3/006 ,  G09G2300/026 ,  G09G2320/10 ,  G09G2360/122 ,  G09G2370/18 ,  G09G2370/22

摘要： An image display device includes a display unit that includes a plurality of display lines, an image data input unit that receives image data including data for each display line, and an image data transmission switching circuit that transmits the image data to the display unit.

公开(公告)号：US20140040507A1

公开(公告)日：2014-02-06

申请号：US14053255

申请日：2013-10-14

申请人： Micron Technology, Inc.

发明人： Victor Tsai ,  William Henry Radke ,  Bob Leibowitz

IPC分类号： G06F11/30

CPC分类号： G06F12/1081 ,  G06F3/007 ,  G06F11/3034 ,  G06F13/16 ,  G06F13/28 ,  G06F13/4063 ,  G06F13/4208 ,  G06F13/4234

摘要： Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

摘要翻译： 描述和示出了能够在链中配置的存储器件和方法。 在一个配置中，主机使用单个数据输入端口和单个数据输出端口与存储器设备链路进行通信。 描述了将标识符分配给链中的存储器件的方法，其包括检测下游存储器件的存在或不存在。 在所选择的示例中，标识符被顺序地分配给链中的存储设备，直到没有检测到附加的下游存储器设备。

公开(公告)号：US4106109A

公开(公告)日：1978-08-08

申请号：US764603

申请日：1977-02-01

申请人： Charles J. Fassbender

发明人： Charles J. Fassbender

IPC分类号： G11C11/41 ,  G06F3/00 ,  G06F12/06 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C8/02

CPC分类号： G11C11/407 ,  G06F3/007 ,  G11C11/4096

摘要： The disclosed random access memory (RAM) for digital data includes the normal data input circuit, a memory matrix for storing applied data, address control circuits for selectively addressing any cell of the memory matrix, and a data output circuit for selectively applying digital data stored in the memory matrix to a data output line. To achieve a high digital data output rate, a rate substantially higher than the rate at which the cells of the memory can be addressed, the improved RAM includes a data output register having a multiplicity of data storage elements and means for simultaneously reading digital data stored in the memory matrix in parallel into the data storage elements of the output register. This data then is selectively applied to the data output line while new data is being addressed in the memory matrix. Thus, data may be accessed in the memory matrix of the RAM at the normal, relatively slow rate while data previously loaded into the output register is read to the data output line at a relatively high rate.

摘要翻译： 所公开的用于数字数据的随机存取存储器（RAM）包括正常数据输入电路，用于存储应用数据的存储矩阵，用于选择性寻址存储器矩阵的任何单元的地址控制电路，以及用于选择性地应用存储的数字数据的数据输出电路 在存储矩阵中将数据输出线。 为了实现高数字数据输出速率，速率明显高于可以寻址存储器单元的速率，改进的RAM包括具有多个数据存储元件的数据输出寄存器和用于同时读取存储的数字数据的装置 在存储器矩阵中并行输入寄存器的数据存储元件。 该数据然后被选择性地施加到数据输出线，同时在存储器矩阵中寻址新的数据。 因此，可以以正常的，相对较慢的速率在RAM的存储器矩阵中访问数据，同时预先加载到输出寄存器中的数据以相对高的速率读取到数据输出线。

公开(公告)号：US3798607A

公开(公告)日：1974-03-19

申请号：US3798607D

申请日：1972-12-01

申请人： MONSANTO CO

发明人： MINNICK R ,  SEMON W ,  BAILEY P ,  SANDFORT R

IPC分类号： G06F3/00 ,  G06F9/315 ,  G06F9/40 ,  G11C19/08 ,  H03K19/168 ,  G11C11/02

CPC分类号： G06F9/30032 ,  G06F3/007 ,  G06F9/4425 ,  G11C19/0875 ,  H03K19/168

摘要： In a general purpose computer system operating on a fetchexecute cycle, arithmetic, logic, storage and control functions are carried out by means of magnetic bubble circuits. A plurality of logic sub-systems called modules are interconnected by a closed unidirectional buss permitting intermodule transfer of data in the form of magnetic bubbles. The memory for the computer consists of a plurality of serial shift registers called marktime lines each comprising a chain of recirculating loops. On signal, data can be advanced in series around the chain. Modules in one subset are specialized to perform various functions. The remaining modules constitute logic interfaces between corresponding mark-time lines and the special subset of modules. All instructions include designating an intermodule transfer or of initiating a search for a storage location in a mark-time line.

摘要翻译： 在通过读取执行周期工作的通用计算机系统中，通过磁性气泡电路来执行算术，逻辑，存储和控制功能。 称为模块的多个逻辑子系统通过封闭的单向总线互连，允许以磁性气泡的形式进行数据的模块间传送。 用于计算机的存储器由称为标记时间线的多个串行移位寄存器组成，每个包括循环回路链。 在信号上，数据可以串连在一起。 一个子集中的模块专门用于执行各种功能。 剩余的模块构成对应的标记时间线和模块的特殊子集之间的逻辑接口。 所有指令包括指定模块间传输或启动在标记时间行中搜索存储位置。

公开(公告)号：US3732550A

公开(公告)日：1973-05-08

申请号：US3732550D

申请日：1970-12-23

申请人： BAYER AG

发明人： HAUPT W

IPC分类号： G06F3/00 ,  G11C11/06 ,  G11C11/04

CPC分类号： G06F3/007 ,  G11C11/06007

摘要： A bistable storage element with magnetic data storage contains in its magnetic circuit magnetized cores with different coercivities H1 and H2 so that only one core can be remagnetized by an external magnetic field H of the value H2

摘要翻译： 具有磁数据存储器的双稳态存储元件在其磁路中包含具有不同矫顽力H1和H2的磁化磁芯，使得只有一个磁芯可以由值H2

公开(公告)号：US3566097A

公开(公告)日：1971-02-23

申请号：US3566097D

申请日：1967-03-06

申请人： TELEFUNKEN PATENT

发明人： HILDEBRANDT VOLKER

IPC分类号： G06F3/00 ,  G06F3/02 ,  G06F15/02 ,  G11C21/00 ,  G06F7/38 ,  G06F13/02 ,  G06F15/00

CPC分类号： G06F3/007 ,  G06F3/0227 ,  G06F15/02 ,  G11C21/00

摘要： An electronic calculator for performing arithmetic operations on binary coded numbers using delay line storage techniques. Four dynamic storage positions are defined in a single channel delay line storage loop by means of timing pulses, and binary coded numbers are introduced into and extracted from the delay line storage loop through a shift register which is coupled to an adder circuit. Binary coded numbers are stored in the delay line storage loop in accordance with an interspersed serial code in which each bit of each binary number is adjacent in the time sequence to the corresponding bit of a different binary number, whereby the consecutive bits of each binary number are separated from each other in the time sequence and are interspersed among the individual bits of other binary numbers. This interspersed serial code allows the delay line storage loop to be operated at a substantially higher bit rate than the shift register and adder circuit, thereby materially reducing the size and cost of the delay line, shift register and adder circuits.

公开(公告)号：US20170199828A1

公开(公告)日：2017-07-13

申请号：US15470590

申请日：2017-03-27

申请人： Micron Technology, Inc

发明人： Victor Tsai ,  William Henry Radke ,  Bob Leibowitz

IPC分类号： G06F12/1081 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F13/28 ,  G06F11/30 ,  G06F3/00

CPC分类号： G06F12/1081 ,  G06F3/007 ,  G06F11/3034 ,  G06F13/16 ,  G06F13/28 ,  G06F13/4063 ,  G06F13/4208 ,  G06F13/4234

摘要： Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

公开(公告)号：US08560735B2

公开(公告)日：2013-10-15

申请号：US12192450

申请日：2008-08-15

申请人： Victor Tsai ,  William Henry Radke ,  Bob Leibowitz

发明人： Victor Tsai ,  William Henry Radke ,  Bob Leibowitz

IPC分类号： G06F3/00

CPC分类号： G06F12/1081 ,  G06F3/007 ,  G06F11/3034 ,  G06F13/16 ,  G06F13/28 ,  G06F13/4063 ,  G06F13/4208 ,  G06F13/4234

摘要： Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

摘要翻译： 描述和示出了能够在链中配置的存储器件和方法。 在一个配置中，主机使用单个数据输入端口和单个数据输出端口与存储器设备链路进行通信。 描述了将标识符分配给链中的存储器件的方法，其包括检测下游存储器件的存在或不存在。 在所选择的示例中，标识符被顺序地分配给链中的存储设备，直到没有检测到附加的下游存储器设备。

公开(公告)号：US4710895A

公开(公告)日：1987-12-01

申请号：US731487

申请日：1985-05-07

申请人： Harumi Maegawa ,  Sakan Takai ,  Toshiaki Sukeda ,  Shoji Irie ,  Shoichi Kobata

发明人： Harumi Maegawa ,  Sakan Takai ,  Toshiaki Sukeda ,  Shoji Irie ,  Shoichi Kobata

IPC分类号： G06F3/00 ,  G11B11/14 ,  G11C11/14 ,  G11C19/08 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： G06F3/007 ,  G11C11/14 ,  G11C19/085 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10977 ,  H05K3/3447 ,  H05K3/368

摘要： A magnetic bubble memory module containing a magnetic bubble memory device and its analog peripheral circuits mounted on a substrate, having outer input/output lead terminals, allowing the module to be mounted on a conventional printed circuit board instantaneously with other electronic elements. Lead terminals of the magnetic bubble memory device are protected by a protection means of an insulator such as plastic material, so that the magnetic bubble memory device is protected from the electrostatic discharge damage caused by the touching of a charged body such as human fingers. This results in high reliability and high production yield of the magnetic bubble memory apparatus.

摘要翻译： 一个磁性气泡存储器模块，其包含安装在基板上的磁性气泡存储器件及其模拟外围电路，具有外部输入/输出引线端子，允许模块与其它电子元件瞬时地安装在常规印刷电路板上。 磁性气泡存储装置的引线端子由诸如塑料材料的绝缘体的保护装置保护，使得磁性气泡存储装置得到保护，免受由人体手指等带电体的触摸而引起的静电放电损坏。 这导致磁性气泡存储装置的高可靠性和高生产率。