公开(公告)号：US20180329685A1

公开(公告)日：2018-11-15

申请号：US15594223

申请日：2017-05-12

Applicant: Google Inc.

Inventor： Artem VASILYEV ,  Albert MEIXNER ,  Jason REDGRAVE

IPC: G06F7/50 ,  G11C19/38 ,  G06T1/20

CPC classification number: G06F7/50 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30134 ,  G06F9/3893 ,  G06T1/20 ,  G11C19/38

Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

公开(公告)号：US20180330465A1

公开(公告)日：2018-11-15

申请号：US15595242

申请日：2017-05-15

Applicant: Google Inc.

Inventor： Jason REDGRAVE ,  Albert MEIXNER ,  Qiuling ZHU ,  Ji KIM ,  Artem VASILYEV ,  Ofer SHACHAM

IPC: G06T1/20 ,  G06F12/0813 ,  H04L25/40 ,  G06F15/80

CPC classification number: G06T1/20 ,  G06F12/0813 ,  G06F15/8023 ,  H04L25/40

Abstract: A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.

公开(公告)号：US20180329864A1

公开(公告)日：2018-11-15

申请号：US15594502

申请日：2017-05-12

Applicant: Google Inc.

Inventor： Jason REDGRAVE ,  Albert MEIXNER ,  Ji KIM ,  Ofer SHACHAM

IPC: G06F15/80 ,  G06T1/20

Abstract: A method is described. The method includes configuring a first instance of object code to execute on a processor. The processor has multiple cores and an internal network. The internal network is configured in a first configuration that enables a first number of the cores to be communicatively coupled. The method also includes configuring a second instance of the object code to execute on a second instance of the processor. A respective internal network of the second instance of the processor is configured in a second configuration that enables a different number of cores to be communicatively coupled, wherein, same positioned cores on the processor and the second instance of the processor have same network addresses for the first and second configurations. A processor is also described having an internal network designed to enable the above method.

公开(公告)号：US20180329863A1

公开(公告)日：2018-11-15

申请号：US15595316

申请日：2017-05-15

Applicant: Google Inc.

Inventor： Asif KHAN ,  Jason REDGRAVE ,  Neeti DESAI ,  David WARREN

IPC: G06F15/78 ,  G06T1/20

CPC classification number: G06F15/78 ,  G06F15/7867 ,  G06T1/20

Abstract: An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format from a camera. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.