公开(公告)号：US20170249717A1

公开(公告)日：2017-08-31

申请号：US15427374

申请日：2017-02-08

Applicant: Google Inc.

Inventor： Albert MEIXNER ,  Hyunchul PARK ,  Qiuling ZHU ,  Jason Rupert REDGRAVE

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/3887 ,  G06T1/20

Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array. The method also includes repeatedly moving a next sheet of image data to be fully loaded into the two dimensional shift register array from a second location of the memory to the first location of the memory.

公开(公告)号：US20180330467A1

公开(公告)日：2018-11-15

申请号：US15594512

申请日：2017-05-12

Applicant: Google Inc.

Inventor： Hyunchul PARK ,  Albert MEIXNER ,  Qiuling ZHU ,  William MARK

IPC: G06T1/60 ,  G06T1/20 ,  G06F3/06

CPC classification number: G06T1/60 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/068 ,  G06F9/5016 ,  G06F12/084 ,  G06F12/0842 ,  G06F17/5009 ,  G06F17/5022 ,  G06F2212/455 ,  G06F2212/601 ,  G06F2217/86 ,  G06T1/20 ,  G09G5/363

Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.

公开(公告)号：US20180330465A1

公开(公告)日：2018-11-15

申请号：US15595242

申请日：2017-05-15

Applicant: Google Inc.

Inventor： Jason REDGRAVE ,  Albert MEIXNER ,  Qiuling ZHU ,  Ji KIM ,  Artem VASILYEV ,  Ofer SHACHAM

IPC: G06T1/20 ,  G06F12/0813 ,  H04L25/40 ,  G06F15/80

CPC classification number: G06T1/20 ,  G06F12/0813 ,  G06F15/8023 ,  H04L25/40

Abstract: A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.