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公开(公告)号：US10108581B1
公开(公告)日：2018-10-23
申请号：US15477791
申请日：2017-04-03
Applicant: Google LLC
Inventor： Gregory Michael Thorson , Andrew Everett Phelps , Olivier Temam
Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.
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公开(公告)号：US20180253403A1
公开(公告)日：2018-09-06
申请号：US15966275
申请日：2018-04-30
Applicant: Google LLC
Inventor： Dong Hyuk Woo , Gregory Michael Thorson , Andrew Everett Phelps , Olivier Temam , Jonathan Ross , Christopher Aaron Clark
IPC: G06F17/16
CPC classification number: G06F17/16 , G06F7/76 , G06F9/30032 , G06F9/30036
Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
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公开(公告)号：US11934826B2
公开(公告)日：2024-03-19
申请号：US17530869
申请日：2021-11-19
Applicant: Google LLC
Inventor： Thomas Norrie , Gurushankar Rajamani , Andrew Everett Phelps , Matthew Leever Hedlund , Norman Paul Jouppi
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/3004 , G06F13/28 , G06F15/7821 , G06N3/045
Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.
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公开(公告)号：US11520581B2
公开(公告)日：2022-12-06
申请号：US17327957
申请日：2021-05-24
Applicant: Google LLC
Inventor： William Lacy , Gregory Michael Thorson , Christopher Aaron Clark , Norman Paul Jouppi , Thomas Norrie , Andrew Everett Phelps
IPC: G06F9/30 , G06F15/80 , G06F9/38 , G06F7/58 , G06F13/36 , G06F13/40 , G06F13/42 , G06F17/16 , G06N3/063 , G06N20/00
Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.
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公开(公告)号：US20210357212A1
公开(公告)日：2021-11-18
申请号：US17327957
申请日：2021-05-24
Applicant: Google LLC
Inventor： William Lacy , Gregory Michael Thorson , Christopher Aaron Clark , Norman Paul Jouppi , Thomas Norrie , Andrew Everett Phelps
Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.
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Patent Agency Ranking
公开(公告)号：US11049016B2
公开(公告)日：2021-06-29
申请号：US16824411
申请日：2020-03-19
Applicant: Google LLC
Inventor： Jonathan Ross , Norman Paul Jouppi , Andrew Everett Phelps , Reginald Clifford Young , Thomas Norrie , Gregory Michael Thorson , Dan Luu
Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.
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公开(公告)号：US20210124795A1
公开(公告)日：2021-04-29
申请号：US17093439
申请日：2020-11-09
Applicant: Google LLC
Inventor： Andrew Everett Phelps , Norman Paul Jouppi
Abstract: Methods, systems, and apparatus for performing a matrix multiplication using a hardware circuit are described. An example method begins by obtaining an input activation value and a weight input value in a first floating point format. The input activation value and the weight input value are multiplied to generate a product value in a second floating point format that has higher precision than the first floating point format. A partial sum value is obtained in a third floating point format that has a higher precision than the first floating point format. The partial sum value and the product value are combined to generate an updated partial sum value that has the third floating point format.
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公开(公告)号：US20200327186A1
公开(公告)日：2020-10-15
申请号：US16915286
申请日：2020-06-29
Applicant: Google LLC
Inventor： Andrew Everett Phelps , Norman Paul Jouppi
Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.
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公开(公告)号：US10706007B2
公开(公告)日：2020-07-07
申请号：US16129663
申请日：2018-09-12
Applicant: Google LLC
Inventor： Gregory Michael Thorson , Andrew Everett Phelps , Olivier Temam
Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.
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公开(公告)号：US20190354571A1
公开(公告)日：2019-11-21
申请号：US16529662
申请日：2019-08-01
Applicant: Google LLC
Inventor： Andrew Everett Phelps , Norman Paul Jouppi
Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.
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