公开(公告)号：US20240281404A1

公开(公告)日：2024-08-22

申请号：US18651933

申请日：2024-05-01

Applicant: Google LLC

Inventor： Kyle Nesbit ,  Andrew Everett Phelps

IPC: G06F15/173 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

公开(公告)号：US11989258B2

公开(公告)日：2024-05-21

申请号：US17093439

申请日：2020-11-09

Applicant: Google LLC

Inventor： Andrew Everett Phelps ,  Norman Paul Jouppi

IPC: G06F17/16 ,  G06F7/483 ,  G06F7/487 ,  G06F9/30 ,  G06N3/02 ,  G06N3/048 ,  G06N3/063

CPC classification number: G06F17/16 ,  G06F7/483 ,  G06F7/4876 ,  G06F9/30014 ,  G06N3/02 ,  G06N3/048 ,  G06N3/063

Abstract: Methods, systems, and apparatus for performing a matrix multiplication using a hardware circuit are described. An example method begins by obtaining an input activation value and a weight input value in a first floating point format. The input activation value and the weight input value are multiplied to generate a product value in a second floating point format that has higher precision than the first floating point format. A partial sum value is obtained in a third floating point format that has a higher precision than the first floating point format. The partial sum value and the product value are combined to generate an updated partial sum value that has the third floating point format.

公开(公告)号：US11620513B2

公开(公告)日：2023-04-04

申请号：US16593321

申请日：2019-10-04

Applicant: Google LLC

Inventor： Jonathan Ross ,  Andrew Everett Phelps

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06N5/04 ,  G06N3/02

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computing a layer output for a convolutional neural network layer, the method comprising: receiving the layer input, the layer input comprising a plurality of activation inputs, the plurality of activation inputs represented as a multi-dimensional matrix comprising a plurality of depth levels, each depth level being a respective matrix of distinct activation inputs from the plurality of activation inputs; sending each respective kernel matrix structure to a distinct cell along a first dimension of the systolic array; for each depth level, sending the respective matrix of distinct activation inputs to a distinct cell along a second dimension of the systolic array; causing the systolic array to generate an accumulated output from the respective matrices sent to the cells; and generating the layer output from the accumulated output.

公开(公告)号：US20220366255A1

公开(公告)日：2022-11-17

申请号：US17874573

申请日：2022-07-27

Applicant: Google LLC

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06F15/80 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20210209193A1

公开(公告)日：2021-07-08

申请号：US17210293

申请日：2021-03-23

Applicant: Google LLC

Inventor： Andrew Everett Phelps ,  Norman Paul Jouppi

IPC: G06F17/16 ,  G06F5/01 ,  G06F9/30 ,  G06F15/80

Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

公开(公告)号：US10956537B2

公开(公告)日：2021-03-23

申请号：US16840972

申请日：2020-04-06

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam ,  Jonathan Ross ,  Christopher Aaron Clark

IPC: G06F17/16 ,  G06F7/76 ,  G06F9/30 ,  G06N3/063 ,  G06N3/08

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

公开(公告)号：US20210019618A1

公开(公告)日：2021-01-21

申请号：US16915161

申请日：2020-06-29

Applicant: Google LLC

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06F15/80 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20200301996A1

公开(公告)日：2020-09-24

申请号：US16840972

申请日：2020-04-06

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam ,  Jonathan Ross ,  Christopher Aaron Clark

IPC: G06F17/16 ,  G06F7/76 ,  G06F9/30

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

公开(公告)号：US20190205141A1

公开(公告)日：2019-07-04

申请号：US16298535

申请日：2019-03-11

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC: G06F9/355 ,  G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F17/16 ,  G06F9/32

CPC classification number: G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US20180336456A1

公开(公告)日：2018-11-22

申请号：US15983056

申请日：2018-05-17

Applicant: Google LLC

Inventor： Thomas Norrie ,  Olivier Temam ,  Andrew Everett Phelps ,  Norman Paul Jouppi

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/08

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30141 ,  G06F9/3885 ,  G06F15/76 ,  G06N3/00

Abstract: Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.