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公开(公告)号：US10304156B2
公开(公告)日：2019-05-28
申请号：US15625972
申请日：2017-06-16
Applicant: Google LLC
Inventor： Albert Meixner , Hyunchul Park , Qiuling Zhu , Jason Rupert Redgrave
Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
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公开(公告)号：US09978116B2
公开(公告)日：2018-05-22
申请号：US15598082
申请日：2017-05-17
Applicant: Google LLC
Inventor： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William Mark , Jason Rupert Redgrave , Ofer Shacham
CPC classification number: G06T1/20 , G06K9/00986 , G11C19/28
Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
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公开(公告)号：US20200275040A1
公开(公告)日：2020-08-27
申请号：US16859308
申请日：2020-04-27
Applicant: Google LLC
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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公开(公告)号：US20200257639A1
公开(公告)日：2020-08-13
申请号：US16518503
申请日：2019-07-22
Applicant: Google LLC
Inventor： Vinod Chamarty , Xiaoyu Ma , Hongil Yoon , Keith Robert Pflederer , Weiping Liao , Benjamin Dodge , Albert Meixner , Allan Douglas Knies , Manu Gulati , Rahul Jagdish Thakur , Jason Rupert Redgrave
IPC: G06F13/16 , G06F12/0815 , G06F12/0877 , G06F12/0811
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.
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公开(公告)号：US10719295B2
公开(公告)日：2020-07-21
申请号：US16687488
申请日：2019-11-18
Applicant: Google LLC
Inventor： Artem Vasilyev , Albert Meixner , Jason Rupert Redgrave
Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.
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Patent Agency Ranking
公开(公告)号：US20200186667A1
公开(公告)日：2020-06-11
申请号：US16786359
申请日：2020-02-10
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Qiuling Zhu , Daniel Frederic Finchelstein
Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
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公开(公告)号：US20190378239A1
公开(公告)日：2019-12-12
申请号：US16547801
申请日：2019-08-22
Applicant: Google LLC
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US10321077B2
公开(公告)日：2019-06-11
申请号：US15598027
申请日：2017-05-17
Applicant: Google LLC
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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公开(公告)号：US10291813B2
公开(公告)日：2019-05-14
申请号：US14694806
申请日：2015-04-23
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Qiuling Zhu , Daniel Frederic Finchelstein
Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
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公开(公告)号：US10275253B2
公开(公告)日：2019-04-30
申请号：US15595632
申请日：2017-05-15
Applicant: Google LLC
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
Abstract: An apparatus that includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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