公开(公告)号：US20200159494A1

公开(公告)日：2020-05-21

申请号：US16687488

申请日：2019-11-18

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Albert Meixner ,  Jason Rupert Redgrave

IPC: G06F7/50 ,  G06T1/20 ,  G11C19/38 ,  G06F9/38 ,  G06F9/30

Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

公开(公告)号：US10719295B2

公开(公告)日：2020-07-21

申请号：US16687488

申请日：2019-11-18

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Albert Meixner ,  Jason Rupert Redgrave

IPC: G06F7/50 ,  G06T1/20 ,  G11C19/38 ,  G06F9/30 ,  G06F9/38

Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

公开(公告)号：US10185560B2

公开(公告)日：2019-01-22

申请号：US15591955

申请日：2017-05-10

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

公开(公告)号：US20220206796A1

公开(公告)日：2022-06-30

申请号：US17691615

申请日：2022-03-10

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

IPC: G06F9/30 ,  G06F7/57 ,  G06F9/38 ,  G06F15/80

Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

公开(公告)号：US10481870B2

公开(公告)日：2019-11-19

申请号：US15594223

申请日：2017-05-12

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Albert Meixner ,  Jason Redgrave

IPC: G06F7/50 ,  G11C19/38 ,  G06T1/20

Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.

公开(公告)号：US20190213006A1

公开(公告)日：2019-07-11

申请号：US16251887

申请日：2019-01-18

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/80

Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.