公开(公告)号：US12073216B1

公开(公告)日：2024-08-27

申请号：US18109583

申请日：2023-02-14

Applicant: Google LLC

Inventor： Matthew Leever Hedlund ,  Christopher Aaron Clark ,  Andrew Everett Phelps ,  Thomas James Norrie ,  Sushma Honnavara-Prasad ,  Vinayak Anand Gokhale ,  Pareesa Ameneh Golnari

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F17/16

Abstract: In a system including vector registers storing right-hand side data and left-hand side data, first and second matrix staging registers, and a systolic array of processing cells for conducting matrix multiplication operations using the right-hand side data and left-hand side data, one or more processors load the right-hand side data from the vector registers to the first matrix staging register based on an instruction indicating whether to transpose the right-hand side data, load the left-hand side data from the vector registers into the second matrix staging register based on another instruction indicating whether to transpose the left-hand side data, load the right-hand side data from the first matrix staging register into the systolic array, and, in a cycle of the matrix multiplication operation, pass one or more columns of the left-hand side data from the second matrix staging register to a column of the systolic array.

公开(公告)号：US20240220202A1

公开(公告)日：2024-07-04

申请号：US18168972

申请日：2023-02-14

Applicant: Google LLC

Inventor： Matthew Leever Hedlund ,  Christopher Aaron Clark ,  Andrew Everett Phelps ,  Thomas James Norrie ,  Norman Paul Jouppi ,  Sushma Honnavara-Prasad ,  Vinayak Anand Gokhale ,  Pareesa Ameneh Golnari

IPC: G06F7/544 ,  G06F7/485 ,  G06F7/487 ,  G06F15/80

CPC classification number: G06F7/5443 ,  G06F7/485 ,  G06F7/4876 ,  G06F15/8046

Abstract: A system and method for matrix multiplication using a systolic array configurable between multiple modes of operation. A systolic processor may receive a data type indicator for the matrix multiplication. For a first data type, the systolic processor may load the right-hand side data from the right-hand matrix register into the data processing cells of the systolic array between row 0 and row M−1, and pass the respective row of the left-hand side data through a corresponding row of the systolic array between rows 0 and M−1. For a second data type, the systolic processor may split each element of the left-hand side data and the right-hand side data into respective first and second element halves, and move each element half through a corresponding row of the systolic array between rows 0 and 2M−1.

公开(公告)号：US20230297152A1

公开(公告)日：2023-09-21

申请号：US18201974

申请日：2023-05-25

Applicant: Google LLC

Inventor： Houle Gan ,  Thomas James Norrie ,  Gregory Sizikov ,  Georgios Konstadinidis

IPC: G06F1/28 ,  G06N20/00

CPC classification number: G06F1/28 ,  G06N20/00

Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.