Abstract:
A method of classifying the defects on a wafer having some same chips and corresponding system is provided. After receiving images formed by scanning the wafer using a charged particle beam, these images are examined such that both defective images and defect-free images are found. Then, the defect-free images are translated into a simulated layout of the chip, or a database is used to provide the simulated layout of the chip. Finally, the defects on the defective images are classified by comparing the images with the simulated layout of the chip. The system has some modules separately corresponds to the steps of the method.
Abstract:
A method for identifying, inspecting, and reviewing all hot spots on a specimen is disclosed by using at least one SORIL e-beam tool. A full die on a semiconductor wafer is scanned by using a first identification recipe to obtain a full die image of that die and then design layout data is aligned and compared with the full die image to identify hot spots on the full die. Threshold levels used to identify hot spots can be varied and depend on the background environments close thereto, materials of the specimens, defect types, and design layout data. A second recipe is used to selectively inspect locations of all hot spots to identify killers, and then killers can be reviewed with a third recipe.
Abstract:
A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.
Abstract:
A method for identifying, inspecting, and reviewing all hot spots on a specimen is disclosed by using at least one SORIL e-beam tool. A full die on a semiconductor wafer is scanned by using a first identification recipe to obtain a full die image of that die and then design layout data is aligned and compared with the full die image to identify hot spots on the full die. Threshold levels used to identify hot spots can be varied and depend on the background environments close thereto, materials of the specimens, defect types, and design layout data. A second recipe is used to selectively inspect locations of all hot spots to identify killers, and then killers can be reviewed with a third recipe.