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公开(公告)号：US10090030B1
公开(公告)日：2018-10-02
申请号：US15581159
申请日：2017-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar , Brent Buchanan
Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.
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公开(公告)号：US10055383B1
公开(公告)日：2018-08-21
申请号：US15581110
申请日：2017-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar
IPC: G06F7/32 , G06F17/16 , G11C11/24 , G11C11/4096 , G11C13/00
CPC classification number: G06F17/16 , G11C7/1006 , G11C8/16 , G11C11/24 , G11C11/4087 , G11C11/4093 , G11C11/4096 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/79
Abstract: A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.
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公开(公告)号：US20180113649A1
公开(公告)日：2018-04-26
申请号：US15571340
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar
CPC classification number: G06F3/0659 , G06F3/0613 , G06F3/0656 , G06F3/0688 , G06F13/16 , G06N3/063 , G11C7/1006 , G11C7/1039 , G11C13/0002 , G11C13/0023
Abstract: In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.
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