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    PERSISTENT TICKET OPERATION
    11.
    发明申请
    PERSISTENT TICKET OPERATION 有权

    公开(公告)号：US20180095783A1

    公开(公告)日：2018-04-05

    申请号：US15333820

    申请日：2016-10-25

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Mark Lillibridge ,  Milind M. Chabbi ,  Haris Volos

    IPC: G06F9/46 ,  G06F9/30

    Abstract: In one example in accordance with the present disclosure, a method may include performing a transactional operation such that if one step of the transactional operation is performed, each other step of the transactional operation is performed. The transactional operation may include making a first copy, stored in a first persistent memory, of a next ticket number stored in a second persistent memory and updating the next ticket number in the second persistent memory. The method may also include determining when to serve a first thread based on the first copy of the next ticket number.

    DETERMINING CACHE VALUE CURRENCY USING PERSISTENT MARKERS
    13.
    发明申请
    DETERMINING CACHE VALUE CURRENCY USING PERSISTENT MARKERS 审中-公开

    公开(公告)号：US20190121750A1

    公开(公告)日：2019-04-25

    申请号：US15789431

    申请日：2017-10-20

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Kimberly Keeton ,  Yupu Zhang ,  Haris Volos ,  Ram Swaminathan ,  Evan R. Kirshenbaum

    IPC: G06F12/14 ,  G06F12/128

    Abstract: Determining cache value currency using persistent markers is disclosed herein. In one example, a cache entry is retrieved from a local cache memory device. The cache entry includes a key, a value to be used by the computing device, and a marker flag to determine whether the cache entry is current. The local cache memory device also includes a marker location that indicates a location of a marker in a shared persistent fabric-attached memory (FAM). Using a marker location, the marker is retrieved from the shared persistent FAM. From the marker and the marker flag, it is determined whether the cache entry is current. The shared FAM pool is connected to the local cache memory devices of multiple computing devices.

    WRITE-AHEAD LOGGING THROUGH A PLURALITY OF LOGGING BUFFERS USING NVM
    16.
    发明申请
    WRITE-AHEAD LOGGING THROUGH A PLURALITY OF LOGGING BUFFERS USING NVM 审中-公开

    公开(公告)号：US20180300083A1

    公开(公告)日：2018-10-18

    申请号：US15485399

    申请日：2017-04-12

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Haris Volos ,  Hideaki Kimura ,  James Park ,  Daniel Fryer

    IPC: G06F3/06

    Abstract: An example system for write-ahead logging through a plurality of logging buffers using a non-volatile memory (NVM) is disclosed. The example disclosed herein comprises a processing unit coupled to one or more controllers from one or more client applications. The example also comprises a plurality of logging buffers to receive a plurality of first log data threads based on a predetermined timestamp range, wherein each log buffer stores a single first timestamp log data thread from a plurality of timestamp log data threads. The example further comprises a flusher to flush the plurality of first timestamp log data threads from the plurality of logging buffers to a first timestamp log data. The flusher stores the first timestamp log data to an NVM to build flushed timestamp log data. The example further comprises a syncer to sync the flushed timestamp log data from the NVM to an HD device in time stamp sequential order.

    Programming model and framework for providing resilient parallel tasks
    18.
    发明授权
    Programming model and framework for providing resilient parallel tasks 有权

    公开(公告)号：US10942824B2

    公开(公告)日：2021-03-09

    申请号：US16153833

    申请日：2018-10-08

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Haris Volos ,  Kimberly Keeton ,  Sharad Singhal ,  Yupu Zhang

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G06F9/48

    Abstract: Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.

    CONCURRENT READING AND WRITING WITH CRASH RECOVERY IN PERSISTENT MEMORY
    19.
    发明申请
    CONCURRENT READING AND WRITING WITH CRASH RECOVERY IN PERSISTENT MEMORY 有权

    公开(公告)号：US20210034281A1

    公开(公告)日：2021-02-04

    申请号：US16529142

    申请日：2019-08-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Milind M. Chabbi ,  Yupu Zhang ,  Haris Volos ,  Kimberly Keeton

    IPC: G06F3/06 ,  G06F12/1081 ,  G06F12/1072

    Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.

    INVARIANT DETERMINATION
    20.
    发明申请
    INVARIANT DETERMINATION 审中-公开

    公开(公告)号：US20180314574A1

    公开(公告)日：2018-11-01

    申请号：US15581882

    申请日：2017-04-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Daniel Fryer ,  James Park ,  Haris Volos

    IPC: G06F11/07

    CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0787

    Abstract: Examples disclosed herein relate to determining that an operation is accessing data on a persistent memory and retrieving a log of the operation. The examples may also include determining a type of the data being accessed by the persistent memory by the operation and identifying, from the log, a location in the persistent memory of the data accessed by the operation. The examples may also include determining contents of the data accessed by the persistent memory by the operation and determining whether the contents of the data hold an invariant corresponding to the type of data.

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