公开(公告)号：US10970213B2

公开(公告)日：2021-04-06

申请号：US16399455

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thomas McGee ,  Michael S. Woodacre ,  Michael Malewicki

IPC: G06F12/0815

Abstract: An apparatus, system, and method of enforcing cache coherency in a multiprocessor shared memory system are disclosed. A request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, a hardware-based cache coherency of the system is disabled, and request is processed according to software-based cache coherency protocols and mechanisms. A coherent read request may be translated to a non-coherent request, such as an immediate read request, which does not trigger tracking or storing state and ownership information of the requested memory block, or trigger communications with processors other than those involved with request. Processing a coherent write request may include transmitting an exclusive read request, which is a request for ownership of the memory block identified in the coherent write request, and transmitting a write acknowledgment to the node controller.

公开(公告)号：US12282662B2

公开(公告)日：2025-04-22

申请号：US17898189

申请日：2022-08-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Thomas Edward McGee ,  Brian J. Johnson ,  Frank R. Dropps ,  Derek S. Schumacher ,  Stuart C. Haden ,  Michael S. Woodacre

IPC: G06F3/06 ,  G06F12/0817

Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.

公开(公告)号：US11687459B2

公开(公告)日：2023-06-27

申请号：US17230286

申请日：2021-04-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/14 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/1441

Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US11586541B2

公开(公告)日：2023-02-21

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/08 ,  G06F13/40 ,  G06F12/0815

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US20220035742A1

公开(公告)日：2022-02-03

申请号：US16944905

申请日：2020-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Schumacher ,  Randy Passint ,  Thomas McGee ,  Michael Malewicki ,  Michael S. Woodacre

IPC: G06F12/0815 ,  G06F13/40

Abstract: One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

公开(公告)号：US20200349075A1

公开(公告)日：2020-11-05

申请号：US16399455

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thomas McGee ,  Michael S. Woodacre ,  Michael Malewicki

IPC: G06F12/0815

Abstract: In exemplary aspects of enforcing cache coherency, a request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, the hardware-based cache coherency of the system is disabled. Instead, the request is processed according to software-based cache coherency mechanisms. A response to the request is transmitted to the requestor.