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公开(公告)号：US20220020324A1
公开(公告)日：2022-01-20
申请号：US17333483
申请日：2021-05-28
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Pan XU
IPC: G09G3/3225 , G11C19/28
Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device. The shift register unit includes: an input circuit, a first capacitor circuit, an output circuit, an output pull-down circuit, a coupling circuit, and an inverter circuit. The inverter circuit is coupled to an input control terminal, a first node, a second node, and a first level signal input terminal, and a second level signal input terminal; and used to control to connect or disconnect the second node and the first level signal input under the control of the input control terminal and the first level signal input terminal; also used to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal.
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公开(公告)号：US20250061851A1
公开(公告)日：2025-02-20
申请号：US18554822
申请日：2023-01-12
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC: G09G3/3233
Abstract: A pixel circuit and a driving method thereof, and a display device are disclosed. The pixel circuit includes a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element. The driving circuit includes a control terminal, a first terminal and a second terminal; the data writing circuit is connected to a first node to apply a data voltage; the reset circuit is connected to the first node to apply a reference voltage. The pixel circuit further includes a partition control circuit, which is connected to the first node and the control terminal, and is configured to apply the data voltage and the reference voltage to the control terminal; the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to the driving circuit.
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公开(公告)号：US20240169925A1
公开(公告)日：2024-05-23
申请号：US17779164
申请日：2021-03-29
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN , Zhongyuan WU
IPC: G09G3/3266 , G09G3/32 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/32 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G11C19/28
Abstract: A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.
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公开(公告)号：US20240233650A1
公开(公告)日：2024-07-11
申请号：US17921677
申请日：2021-11-08
Inventor： Zhidong YUAN , Yongqian LI , Pan XU , Can YUAN
IPC: G09G3/3266 , G09G3/20 , G09G3/3233 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/2096 , G09G3/3233 , G11C19/28 , G09G2300/0819 , G09G2300/0842 , G09G2310/0286 , G09G2310/08 , G09G2340/00
Abstract: A light-emitting control shift register includes an input circuit, a pulse width adjustment circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit. The input circuit is configured to output a signal of a first signal input terminal. The pulse width adjustment circuit is configured to transmit the signal output from the input circuit to a pull-up node, and is further configured to output a signal of a second clock signal terminal to the pull-up node. The pull-up circuit is configured to output a voltage of a first voltage terminal to a signal output terminal. The pull-down control circuit is configured to output the voltage of the first voltage terminal, and is further configured to output a voltage of a second voltage terminal. The pull-down circuit is configured to pull down a voltage of the signal output terminal to the voltage of the second voltage terminal.
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公开(公告)号：US20240203357A1
公开(公告)日：2024-06-20
申请号：US17802580
申请日：2021-04-01
Inventor： Xuehuan FENG , Yongqian LI , Pan XU
IPC: G09G3/3266 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G2300/0426 , G09G2300/0842 , G09G2310/0286 , G09G2310/08
Abstract: A display panel has a display area and a fan-out region. The display panel includes: a substrate; a scan driving circuit including shift registers and clock signal lines, sub-pixels and signal transmission lines that are located in the display area; and a power supply voltage bus and connection lines that are located in the fan-out region. The sub-pixels are arranged in rows and columns, sub-pixels in a column are arranged along a second direction. A signal transmission line is electrically connected to column(s) of sub-pixels. The connection lines include first connection sub-lines, second connection sub-lines and third connection sub-lines that extend along the second direction and are located away from the sub-pixels. A first connection sub-line, a second connection sub-line and a third connection sub-line are electrically connected to the signal transmission line, the power supply voltage bus, and a clock signal line, respectively.
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Patent Agency Ranking
公开(公告)号：US20230122411A1
公开(公告)日：2023-04-20
申请号：US17914466
申请日：2021-11-19
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN , Pan XU
IPC: H10K59/131 , G09G3/3266 , H10K59/121 , H10K59/126 , H10K50/824 , H10K50/813
Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.
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17.发明申请公开(公告)号：US20220406252A1
公开(公告)日：2022-12-22
申请号：US17620195
申请日：2020-12-23
Inventor： Xuehuan FENG , Yongqian LI , Pan XU , Zhongyuan WU
IPC: G09G3/3233 , G09G3/3266
Abstract: A pixel circuit array, a display panel, a method for driving a pixel circuit array, and a method for driving a display panel are provided. The pixel circuit array may include: a first signal sensing line (SENSE1) and a second signal sensing line (SENSE2); and N pixel circuits arranged in a column. All of the N pixel circuits are divided into a first group and a second group, each pixel circuit in the first group is coupled to the first signal sensing line (SENSE1), and each pixel circuit in the second group is coupled to the second signal sensing line (SENSE2) different from the first signal sensing line (SENSE1), where N is a positive integer greater than 1.
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公开(公告)号：US20240179968A1
公开(公告)日：2024-05-30
申请号：US17789210
申请日：2021-07-09
Inventor： Can YUAN , Yongqian LI , Pan XU , Zhidong YUAN , Dacheng ZHANG
IPC: H10K59/131 , G09G3/3225 , H10K59/122
CPC classification number: H10K59/131 , G09G3/3225 , H10K59/122 , G09G2300/0408 , G09G2300/0426 , G09G2300/0452 , G09G2300/0819 , G09G2300/0842 , G09G2310/08
Abstract: A display substrate includes: a substrate and a plurality of subpixels arranged on the substrate, the plurality of subpixels are arranged in an array; the subpixel includes a subpixel driving circuit and a light emitting element, and the subpixel driving circuit includes a driving sub-circuit and a light emitting control sub-circuit coupled to each other; the light emitting element includes an anode pattern; the plurality of subpixels are divided into a plurality of groups of subpixels, each group of subpixels includes two subpixels arranged along a first direction, and two subpixel driving circuits included in the two subpixels share a same light emitting control sub-circuit, the light emitting control sub-circuit is configured to respectively control the driving sub-circuits in the two subpixels to write a driving signal to the anode pattern; the subpixel further includes a data line including a part extending along the first direction.
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公开(公告)号：US20250104646A1
公开(公告)日：2025-03-27
申请号：US18558905
申请日：2023-01-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chengyuan LUO , Pan XU , Ying HAN , Xing ZHANG , Donghui ZHAO , Guangshuang LV , Cheng XU , Xing YAO , Dandan ZHOU , Miao LIU
IPC: G09G3/3266
Abstract: A driving circuit, a driving module, a driving method, a display substrate and a display device are provided. The driving circuit includes a first leakage prevention circuit, an output circuit and a first control node control circuit; the first leakage prevention circuit is configured to control to connect or disconnect the first control node, the first node and the first intermediate node under the control of a first voltage signal provided by the first voltage line according to a potential of the first intermediate node, control to connect or disconnect the first intermediate node and the second voltage line under the control of the potential of the first node, and control to disconnect the first control node and the first node when the first intermediate node and the second voltage line is connected.
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公开(公告)号：US20240212622A1
公开(公告)日：2024-06-27
申请号：US17794994
申请日：2021-08-24
Applicant: BOE Technology Group Co., Ltd.
Inventor： Pan XU , Hongli WANG , Danyang MA , Guoying WANG , Xing ZHANG , Chengyuan LUO , Ying HAN
IPC: G09G3/3266
CPC classification number: G09G3/3266
Abstract: A display substrate includes an underlayer substrate and a circuit structure layer. The circuit structure layer is located in a display area of the underlayer substrate. The circuit structure layer includes at least one first circuit area and at least one second circuit area. The first circuit area includes at least one first gate drive circuit; the second circuit area includes at least one second gate drive circuit. The first gate drive circuit is cascaded with the second gate drive circuit. The first gate drive circuit includes a plurality of cascaded first gate drive units, and the second gate drive circuit includes a plurality of cascaded second gate drive units. A plurality of first gate drive units are sequentially arranged in a second direction, and a plurality of second gate drive units are sequentially arranged in the second direction.
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