公开(公告)号：US20180217929A1

公开(公告)日：2018-08-02

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0607 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US20170185343A1

公开(公告)日：2017-06-29

申请号：US15314710

申请日：2014-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Gary Gostin ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

公开(公告)号：US10664369B2

公开(公告)日：2020-05-26

申请号：US15500063

申请日：2015-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock ,  Harvey Ray ,  Michael Kontz

IPC: G06F11/20 ,  G06F11/07 ,  G06F11/10

Abstract: According to an example, a failed component in a fault-tolerant memory fabric may be determined by transmitting request packets along a plurality of routes between the redundancy controller and a media controller in periodic cycles. The redundancy controller may determine whether route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles. In response to determining that route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles, the media controller is established as failed. In response to determining that route failures for less than all of the plurality of routes have occurred within the number of consecutive periodic cycles, a fabric device is established as failed.

公开(公告)号：US10579519B2

公开(公告)日：2020-03-03

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US10474389B2

公开(公告)日：2019-11-12

申请号：US15201981

申请日：2016-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Brian S. Birk ,  Joseph F. Orth ,  Harvey Ray ,  Craig Warner

IPC: G06F3/06

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

公开(公告)号：US10402113B2

公开(公告)日：2019-09-03

申请号：US15313690

申请日：2014-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06 ,  G06F11/10

Abstract: According to an example, hierarchal stripe locks may be obtained for a source stripe and a destination stripe. In response to receiving data for the source stripe, the data is written from the source stripe to the destination stripe, and the hierarchal stripe locks are released for the source stripe and the destination stripe. In response to receiving the data-migrated token, the hierarchal stripe locks are released for the source stripe and the destination stripe.

公开(公告)号：US10248571B2

公开(公告)日：2019-04-02

申请号：US15234982

申请日：2016-08-11

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Harvey Ray

IPC: G06F12/02 ,  G06F12/0893

Abstract: In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory and a location storer to store a rotation count of the rotation. The system may also include a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address and a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation. The system may also include a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.

公开(公告)号：US20180011660A1

公开(公告)日：2018-01-11

申请号：US15201981

申请日：2016-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Brian S. Birk ,  Joseph F. Orth ,  Harvey Ray ,  Craig Warner

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673 ,  G06F3/0679

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.