公开(公告)号：US08006636B2

公开(公告)日：2011-08-30

申请号：US12177243

申请日：2008-07-22

申请人： Kazuo Terada ,  Kazuo Sakamoto ,  Takeshi Uehara

发明人： Kazuo Terada ,  Kazuo Sakamoto ,  Takeshi Uehara

IPC分类号： B05C11/02 ,  B05B15/04

CPC分类号： H01L21/6715 ,  H01L21/67178 ,  H01L21/68785

摘要： A substrate treatment apparatus of the present invention includes: a holding means for rotatably holding a substrate to be treated; a coating solution supply nozzle for supplying a coating solution onto the front surface of the substrate to be treated held on the holding means; a treatment container with an upper surface open for housing them; an exhaust means for exhausting an atmosphere in the treatment container from the bottom; a multiblade centrifugal fan provided on the inner periphery of the treatment container for flowing airflow on a front surface side of the substrate to the exhaust means; and a controller for controlling the number of rotations of the multiblade centrifugal fan corresponding to the number of rotations of the substrate, wherein the number of rotations of the multiblade centrifugal fan is controlled so that turbulent airflow flowing in a circumferential direction on the front surface of the substrate generated due to the rotation of the substrate is corrected to laminar airflow flowing in a radial direction.

摘要翻译： 本发明的基板处理装置包括：用于可旋转地保持待处理基板的保持装置; 涂布溶液供给喷嘴，用于将涂布溶液供给到保持在保持装置上的被处理基板的前表面上; 处理容器，其上表面打开以容纳它们; 用于从底部排出处理容器中的气氛的排气装置; 设置在处理容器的内周上的多叶离心风扇，用于将衬底的前表面侧的气流流向排气装置; 以及控制器，用于控制与所述基板的旋转数相对应的所述多叶离心风扇的转数，其中所述多叶离心风扇的转数受到控制，使得在圆周方向上流动的湍流气流在 由于基板的旋转而产生的基板被校正成沿径向流动的层流。

公开(公告)号：US20080185370A1

公开(公告)日：2008-08-07

申请号：US12022489

申请日：2008-01-30

申请人： Tetsuo Fukuoka ,  Takahiro Kitano ,  Kazuo Terada

发明人： Tetsuo Fukuoka ,  Takahiro Kitano ,  Kazuo Terada

IPC分类号： G03F7/40 ,  F27D23/00

CPC分类号： F27B17/0025 ,  G03F7/168 ,  H01L21/67109

摘要： A disclosed heating apparatus includes a heating chamber configured to heat a substrate placed in the heating chamber with a heat plate opposing the substrate; a gas stream forming portion that creates a gas stream along a top surface of the substrate in the heating chamber; and a pair of first plate members respectively located between an inner side wall of the heating chamber and a first substrate edge opposing the inner side wall, and between another inner side wall of the heating chamber and a second substrate edge opposing the other inner side wall.

摘要翻译： 所公开的加热装置包括加热室，该加热室被配置为用与基板相对的加热板加热放置在加热室中的基板; 气流形成部分，其沿着所述加热室中的所述基板的顶表面产生气流; 以及分别位于加热室的内侧壁和与内侧壁相对的第一基板边缘之间以及位于加热室的另一内侧壁和与另一内侧壁相对的第二基板边缘之间的一对第一板构件 。

公开(公告)号：US06756087B2

公开(公告)日：2004-06-29

申请号：US10188268

申请日：2002-07-02

申请人： Kazuo Terada

发明人： Kazuo Terada

IPC分类号： B05D306

CPC分类号： G02F1/133711 ,  G02B5/201

摘要： An organic polymer film can be completely decomposed and removed from a substrate surface by exposing the film to ultraviolet radiation having a wavelength of 180 nm or less. Also, ultraviolet radiation not longer than 180 nm in wavelength is scarcely transmitted through a transparent conductive oxide such as ITO and, thus, can be used for eliminating a defective polyimide alignment film formed on a color filter substrate and an array substrate having a transparent electrode pattern of ITO formed on the surface of a pigment portion and a TFT structure, respectively. According to the present invention, the defective alignment film on the substrates can be removed completely without any damage such as discoloring of the pigment portion and/or changing the TFT characteristics.

摘要翻译： 通过将膜暴露于具有180nm以下的波长的紫外线照射，可以将有机聚合物膜完全分解并从基板表面除去。 此外，波长不大于180nm的紫外线辐射几乎不透过诸如ITO的透明导电氧化物，因此可以用于消除形成在滤色器基板上的有缺陷的聚酰亚胺取向膜和具有透明电极的阵列基板 分别在颜料部分和TFT结构的表面上形成ITO的图案。 根据本发明，可以完全去除基板上的不良取向膜，而不会损坏颜料部分的变色和/或改变TFT特性。

公开(公告)号：US06468599B1

公开(公告)日：2002-10-22

申请号：US09464824

申请日：1999-12-17

申请人： Kazuo Terada

发明人： Kazuo Terada

IPC分类号： B05D306

CPC分类号： G02F1/133711 ,  G02B5/201

摘要： An organic polymer film can be completely decomposed and removed from a substrate surface by exposing the film to ultraviolet radiation having a wavelength of 180 nm or less. Also, ultraviolet radiation not longer than 180 nm in wavelength is scarcely transmitted through a transparent conductive oxide such as ITO and, thus, can be used for eliminating a defective polyimide alignment film formed on a color filter substrate and an array substrate having a transparent electrode pattern of ITO formed on the surface of a pigment portion and a TFT structure, respectively. According to the present invention, the defective alignment film on the substrates can be removed completely without any damage such as discoloring of the pigment portion and/or changing the TFT characteristics.

摘要翻译： 通过将膜暴露于具有180nm以下的波长的紫外线照射，可以将有机聚合物膜完全分解并从基板表面除去。 此外，波长不大于180nm的紫外线辐射几乎不透过诸如ITO的透明导电氧化物，因此可以用于消除形成在滤色器基板上的有缺陷的聚酰亚胺取向膜和具有透明电极的阵列基板 分别在颜料部分和TFT结构的表面上形成ITO的图案。 根据本发明，可以完全去除基板上的不良取向膜，而不会损坏颜料部分的变色和/或改变TFT特性。

公开(公告)号：US06329663B1

公开(公告)日：2001-12-11

申请号：US09286072

申请日：1999-04-05

申请人： Kazuo Terada

发明人： Kazuo Terada

IPC分类号： B08B700

CPC分类号： G02B27/0006 ,  B08B7/0057 ,  G02F1/133516

摘要： According to the invention, a cleaning method and a cleaning apparatus are disclosed for removing organic contaminants on a surface of a color filter without damaging pigment portions of the color filter. The cleaning is performed by using a source of ultraviolet radiation having a wavelength equal to or less than 180 nm (most preferably a wavelength of 172 nm), which does not transmit through the transparent electrodes (e.g., ITO film, IZO film or the like), thereby protecting the pigment portions of the color filter. As a result, the glass substrate can be cleaned by the ultraviolet radiation without discoloring the pigment portions of the color filter and the cleaning effect is increased because the exposure time to the ultraviolet radiation is not limited.

摘要翻译： 根据本发明，公开了一种用于去除滤色器表面上的有机污染物的清洁方法和清洁装置，而不损害滤色器的颜料部分。 通过使用不透过透明电极（例如ITO膜，IZO膜等）的波长等于或小于180nm（最优选波长为172nm）的紫外线辐射源进行清洁 ），从而保护滤色器的颜料部分。 结果，可以通过紫外线照射来清洁玻璃基板，而不会使滤色器的颜料部分变色，并且由于对紫外线辐射的曝光时间不受限制，因此清洁效果增加。

公开(公告)号：US6048767A

公开(公告)日：2000-04-11

申请号：US964416

申请日：1997-11-04

申请人： Kazuo Terada

发明人： Kazuo Terada

IPC分类号： H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10808 ,  H01L27/10805

摘要： Disclosed are an improved semiconductor memory cell suitable for high integration and a novel method of fabricating the same. The memory cell has a large capacitance and a small area. The memory cell also has a plurality of bit-lines buried in an isolation region in a semiconductor substrate. The bit-line has a very small width and thickness thereby reducing a parasitic capacity between the bit-line and the semiconductor substrate. The memory cell may further be provided with a noise shielding line. Further, disclosed is a novel memory cell array of a semiconductor memory. The buried bit-line is coupled with a bit-line connecting sub-arrays and both are separated by a insulation film. A plurality of pairs of the bit-lines are arranged in rows. A word-line is coupled with a sub-word line and both are separated by a insulation film. A plurality of pairs of the word-lines are arranged in columns. The memory cells are arranged at the intersections of the buried bit-lines and the word-lines. The memory cells are also alternatively arranged on the adjacent buried bit-lines so that the number of the memory cells arranged on one of the buried bit-lines are reduced.

摘要翻译： 公开了一种适用于高集成度的改进的半导体存储器单元及其制造方法。 存储单元具有大的电容和小的面积。 存储单元还具有埋在半导体衬底中的隔离区域中的多个位线。 位线具有非常小的宽度和厚度，从而减小位线和半导体衬底之间的寄生电容。 存储单元还可以设置有噪声屏蔽线。 此外，公开了一种半导体存储器的新型存储单元阵列。 掩埋位线与位线连接子阵列耦合，并且两者都被绝缘膜隔开。 多对位线排列成行。 字线与子字线耦合，并且两者都被绝缘膜隔开。 多个字线对被排列成列。 存储单元布置在掩埋位线和字线的交点处。 存储单元也交替地布置在相邻的掩埋位线上，使得布置在一个掩埋位线上的存储单元的数量减少。

公开(公告)号：US09076643B2

公开(公告)日：2015-07-07

申请号：US12652794

申请日：2010-01-06

申请人： Takayuki Toshima ,  Kazuo Terada

发明人： Takayuki Toshima ,  Kazuo Terada

IPC分类号： H01L21/02

CPC分类号： H01L21/02057 ,  H01L21/02101

摘要： Disclosed is a supercritical processing apparatus which can suppress the occurrence of pattern collapse, improve the throughput, and prolong a maintenance interval. In the disclosed supercritical processing apparatus to remove a liquid remained on a substrate by a super-critical state processing fluid, a heating unit heats the processing fluid to place the processing fluid into a processing receptacle in a supercritical state, and a cooling mechanism forcibly cools an area capable of transferring the heat to the substrate from the heating unit in order to suppress the liquid from being evaporated from the substrate until the substrate is disposed on a seating unit.

摘要翻译： 公开了一种超临界处理装置，其可以抑制图案崩溃的发生，提高生产量，并延长维护间隔。 在公开的超临界处理装置中，通过超临界状态处理流体去除残留在基板上的液体，加热单元加热处理流体，将处理流体置于超临界状态的处理容器中，冷却机构强制冷却 能够从加热单元将热量传递到基板的区域，以便抑制液体从基板蒸发直到基板设置在就座单元上。

公开(公告)号：US08235061B2

公开(公告)日：2012-08-07

申请号：US12824565

申请日：2010-06-28

申请人： Takayuki Toshima ,  Kazuo Terada ,  Kazuyuki Honda

发明人： Takayuki Toshima ,  Kazuo Terada ,  Kazuyuki Honda

IPC分类号： B08B3/08 ,  B08B3/10

CPC分类号： B08B3/10 ,  H01L21/67057 ,  H01L21/67751 ,  Y10S134/902

摘要： Provided are a substrate processing apparatus and a substrate processing method capable of processing of a substrate using a supercritical fluid without exposing the pattern formed on the substrate to an atmospheric environment. The substrate processing apparatus includes a cleaning bath configured to accommodate a substrate and clean the substrate by flowing a cleaning solution, and a processing vessel configured to accommodate the cleaning bath and process the substrate with a supercritical fluid.

摘要翻译： 提供了一种基板处理装置和基板处理方法，其能够使用超临界流体处理基板，而不将形成在基板上的图案暴露于大气环境。 基板处理装置包括：清洗槽，其配置为容纳基板并通过流动清洁溶液清洁基板;以及处理容器，其构造成容纳清洗槽并用超临界流体处理基板。

公开(公告)号：US20080182217A1

公开(公告)日：2008-07-31

申请号：US12020898

申请日：2008-01-28

申请人： Tetsuo Fukuoka ,  Takahiro Kitano ,  Kazuo Terada

发明人： Tetsuo Fukuoka ,  Takahiro Kitano ,  Kazuo Terada

IPC分类号： F27D15/02 ,  F27D3/00

CPC分类号： F27B17/0025 ,  H01L21/67109 ,  H01L21/67248

摘要： A heating device 1 includes a flat heating chamber 3 provided with a side opening. A substrate W is carried in a horizontal position through the side opening into the processing chamber 3, and is subjected to a heating process in the heating chamber 3. the heating chamber 3 is provided with heating plates 34 and 35 respectively provided with heating elements 34a and 35a, and a cooling mechanism 2 for cooling the heating plates 34 and 35. A controller 7 controls the cooling mechanism such that the heating plates 34 and 35 are cooled after the completion of the heating process for heating the substrate W and before a succeeding substrate W is carried into the heating chamber 3, and controls the heating elements 34a and 35a such that the heating plates 34 and 35 are heated at a processing temperature after the succeeding substrate has been carried into the heating chamber 3.

摘要翻译： 加热装置1包括具有侧开口的平坦加热室3。 基板W通过侧开口在水平位置被运送到处理室3中，并且在加热室3中进行加热处理。 加热室3设置有分别设有加热元件31a和35a的加热板34和35，以及用于冷却加热板34和35的冷却机构2。 控制器7控制冷却机构，使得加热板34和35在完成用于加热基板W的加热过程之后并且在将下一个基板W运送到加热室3之前被冷却，并且控制加热元件34a 和35a，使得加热板34和35在后续基板被运送到加热室3之后的加工温度下被加热。

公开(公告)号：US5760452A

公开(公告)日：1998-06-02

申请号：US732832

申请日：1996-10-15

申请人： Kazuo Terada

发明人： Kazuo Terada

IPC分类号： H01L27/108 ,  H01L29/105 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/10808 ,  H01L27/10805

摘要： Disclosed are an improved semiconductor memory cell suitable for high integration and a novel method of fabricating the same. The memory cell has a large capacitance and a small area. The memory cell also has a plurality of bit-lines buried in an isolation region in a semiconductor substrate. The bit-line has a very small width and thickness thereby reducing a parasitic capacity between the bit-line and the semiconductor substrate. The memory cell may further be provided with a noise shielding line. Further, disclosed is a novel memory cell array of a semiconductor memory. The buried bit-line is coupled with a bit-line connecting sub-arrays and both are separated by a insulation film. A plurality of pairs of the bit-lines are arranged in rows. A word-line is coupled with a sub-word line and both are separated by a insulation film. A plurality of pairs of the word-lines are arranged in columns. The memory cells are arranged at the intersections of the buried bit-lines and the word-lines. The memory cells are also alternatively arranged on the adjacent buried bit-lines so that the number of the memory cells arranged on one of the buried bit-lines are reduced.

摘要翻译： 公开了一种适用于高集成度的改进的半导体存储器单元及其制造方法。 存储单元具有大的电容和小的面积。 存储单元还具有埋在半导体衬底中的隔离区域中的多个位线。 位线具有非常小的宽度和厚度，从而减小位线和半导体衬底之间的寄生电容。 存储单元还可以设置有噪声屏蔽线。 此外，公开了一种半导体存储器的新型存储单元阵列。 掩埋位线与位线连接子阵列耦合，并且两者都被绝缘膜隔开。 多对位线排列成行。 字线与子字线耦合，并且两者都被绝缘膜隔开。 多个字线对被排列成列。 存储单元布置在掩埋位线和字线的交点处。 存储单元也交替地布置在相邻的掩埋位线上，使得布置在一个掩埋位线上的存储单元的数量减少。