摘要:
A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.
摘要:
Finite impulse response filters are commonly used in high speed data communications electronics for reducing error rates in multilevel symbol encoding schemes. Schemes such as pulse amplitude modulation and quadrature amplitude modulation may have higher error rates for symbols with low signal to noise ratios. By selectively updating the tap coefficients of the filter based on the symbols received, a more robust, accurate filter can be built.
摘要:
A digital timing recovery system wherein the rate conversion is independent of the sampling rate, and which may be set in a network mode or a remote mode. The invention includes a transceiver core for processing transmit and receive data at a predetermined baud rate, an analog front end for transmitting and receiving analog signals over a network, a phase detector for generating a phase error estimate and a timing controller for receiving the phase error estimate signal and generating a receive and transmit phase control signal for controlling timing of the analog front end. A selector is provided for selecting a remote mode of operation or a network mode of operation. The analog front end further includes a transmit converter for converting the transmit data at the baud rate to a digital output at a transmit rate and a digital to analog converter for converting the digital output to an analog signal, and an analog to digital converter for converting the analog receive signal to a digital receive signal and a receive converter for converting the digital receive signal at a receive rate to the baud rate. The phase detector includes a channel estimator for generating a coefficient error signal and the timing controller includes a loop filter for producing a control signal for a numerically controlled oscillator that produces a baud interrupt signal and the phase control signals.
摘要:
A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.
摘要:
A light emitting device that can reduce the illuminance unevenness on an illuminated surface. First light flux controlling member 103 controls the distribution of light emitted from light emitting element 102. Second light flux controlling member 105 has second incidence surface 201 onto which the light emitted from first light flux controlling member 103 is incident and second emission surface 202 that is located on a side opposite to second incidence surface 201 and emits the light incident from second incidence surface 201. Also, at least one surface of second incidence surface 201 and second emission surface 202 refracts the light having an optical path on a virtual cross-section including optical axis P1 of light emitting element 102 and being incident onto second incidence surface 201 or second emission surface 202 more to the optical axis P1 side than when being incident onto a plane perpendicular to optical axis P1.
摘要:
A network component comprising a transmitter configured to transmit data at a transmitter phase, a receiver configured to receive data at a receiver, and a phase delay component coupled to the transmitter and the receiver and configured to control the transmitter phase relative to the receiver phase to maintain distortion in the transmitted data below a threshold, wherein the threshold is less than a maximum possible distortion in the transmitted data.
摘要:
Finite impulse response filters are commonly used in high speed data communications electronics for reducing error rates in multilevel symbol encoding schemes. Schemes such as pulse amplitude modulation and quadrature amplitude modulation may have higher error rates for symbols with low signal to noise ratios. By selectively updating the tap coefficients of the filter based on the symbols received, a more robust, accurate filter can be built.
摘要:
High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be different, which leads to a signal skew problem. This document describes a novel way of compensating for differential line skew in data transmission lines.
摘要:
In one embodiment of the invention, a tap-leakage generator includes an error filter and an updater. The error filter filters a decision error provided by the adaptive filter using a leakage factor. The adaptive filter has N taps. The updater updates N equalizer coefficients to the N taps using the filtered decision error. The updater receives N equalizer data from the N taps.
摘要:
A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.