公开(公告)号：US20180102850A1

公开(公告)日：2018-04-12

申请号：US15839380

申请日：2017-12-12

申请人： INPHI CORPORATION

发明人： Oscar Ernesto AGAZZI ,  Diego Ernesto CRIVELLI ,  Hugo Santiago CARRER ,  Mario Rafael HUEDA ,  German Cesar Augusto LUNA ,  Carl GRACE

IPC分类号： H04B10/50 ,  H04B7/005 ,  H04L25/02 ,  H04B3/23 ,  H03M13/41

CPC分类号： H04B10/5059 ,  H03M13/41 ,  H04B1/38 ,  H04B3/235 ,  H04B7/005 ,  H04B7/0456 ,  H04B10/25073 ,  H04B10/2941 ,  H04B10/40 ,  H04B10/6971 ,  H04B2001/0441 ,  H04B2201/709772 ,  H04L5/16 ,  H04L25/0202 ,  H04L25/025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

公开(公告)号：US09900189B2

公开(公告)日：2018-02-20

申请号：US15233557

申请日：2016-08-10

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC分类号： H04L25/03

CPC分类号： H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US09391816B2

公开(公告)日：2016-07-12

申请号：US14462561

申请日：2014-08-19

申请人： Rambus Inc.

发明人： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC分类号： H03H7/30 ,  H04B1/10 ,  H04L27/06 ,  H04L7/00 ,  H04L25/03

CPC分类号： H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

摘要： A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

摘要翻译： 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择，以确定接收到的数据值。

公开(公告)号：US20160142200A1

公开(公告)日：2016-05-19

申请号：US14868721

申请日：2015-09-29

申请人： Rambus Inc.

发明人： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC分类号： H04L7/033 ,  H04L25/03 ,  H04L7/00

CPC分类号： H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

摘要翻译： 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

公开(公告)号：US20150319017A1

公开(公告)日：2015-11-05

申请号：US14795043

申请日：2015-07-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

摘要： An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.

摘要翻译： 一种装置包括多个延迟元件，其被配置为延迟相应的输入信号并输出​​相应的延迟信号。 该装置还包括配置用于基于延迟信号产生多个抽头权重的权重发生器。 该装置还包括抽头控制器，其被配置为如果对应的抽头权重大于预定阈值，则生成与一个或多个抽头权重对应的抽头加权使能信号。 抽头控制器还被配置为基于多个抽头权重的相应抽头权重来生成一组偏置因子。

公开(公告)号：US09148316B2

公开(公告)日：2015-09-29

申请号：US13937925

申请日：2013-07-09

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Tonmoy Shanker Mukherjee

IPC分类号： H04B1/38 ,  H04L5/16 ,  H04L27/10 ,  H04L27/18 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L25/03878 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) circuit includes a first equalization path and a second equalization path. Each equalization path includes a summing node, a first latch, a second latch, a first feedback path, and a second feedback path. The first latch is configured to latch data received from the summing node. The second latch is configured to latch data received from the first latch. The first feedback path is configured to receive data from the second latch and to provide data to the summing node of the equalization path. The second feedback path is configured to receive data from the first latch and to provide data to the summing node of the other equalization path. The second feedback path provides up to a symbol interval for propagation of data between the summing nodes.

摘要翻译： 判决反馈均衡器（DFE）电路包括第一均衡路径和第二均衡路径。 每个均衡路径包括求和节点，第一锁存器，第二锁存器，第一反馈路径和第二反馈路径。 第一锁存器被配置为锁存从求和节点接收到的数据。 第二锁存器被配置为锁存从第一锁存器接收到的数据。 第一反馈路径被配置为从第二锁存器接收数据并且向均衡路径的求和节点提供数据。 第二反馈路径被配置为从第一锁存器接收数据并且向另一个均衡路径的求和节点提供数据。 第二反馈路径提供达到在求和节点之间的数据传播的符号间隔。

公开(公告)号：US20150207649A1

公开(公告)日：2015-07-23

申请号：US14671810

申请日：2015-03-27

申请人： Huawei Technologies Co., Ltd.

发明人： Dongyuan Shi ,  Dongmei He ,  Meng Cai

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H03H21/0012 ,  H03H2021/0041 ,  H03H2021/007 ,  H04L25/03 ,  H04L25/03019 ,  H04L25/03146 ,  H04L2025/03617 ,  H04L2025/03636

摘要： The present invention discloses an adaptive filtering method and system based on an error sub-band. The present invention includes performing analysis filtering processing on an error signal and an input signal to obtain an error sub-band signal and an input sub-band signal respectively; and performing calculation according to the input sub-band signal and the error sub-band signal to obtain a new adaptive filtering weight, and updating a weight in an adaptive filter.

摘要翻译： 本发明公开了一种基于误差子带的自适应滤波方法和系统。 本发明包括对误差信号和输入信号执行分析滤波处理，以分别获得误差子带信号和输入子带信号; 并根据输入的子带信号和误差子带信号进行计算，得到新的自适应滤波权重，并更新自适应滤波器中的权重。

公开(公告)号：US20140105123A1

公开(公告)日：2014-04-17

申请号：US13725549

申请日：2012-12-21

申请人： Thomas J. Kenney ,  Eldad Perahia ,  Shahrnaz Azizi

发明人： Thomas J. Kenney ,  Eldad Perahia ,  Shahrnaz Azizi

IPC分类号： H04L5/00 ,  H04W72/04

CPC分类号： H04L27/2626 ,  H04L1/0002 ,  H04L1/0009 ,  H04L5/0007 ,  H04L5/003 ,  H04L5/0048 ,  H04L5/005 ,  H04L25/0224 ,  H04L25/0228 ,  H04L25/025 ,  H04L25/03019 ,  H04L2025/03617 ,  H04W72/04 ,  H04W72/0453 ,  H04W84/12

摘要： Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of modulation and coding schemes (MCS) available to an orthogonal frequency division multiplexing (OFDM) system, each MCS having an associated pilot dwell time. The apparatus may further comprise a processor circuit coupled to the memory, the processor circuit configured to identify a MCS to communicate a packet using multiple subcarriers of the OFDM system, and retrieve a pilot dwell time associated with the MCS from the memory, the pilot dwell time to indicate when to shift a pilot tone between subcarriers of the multiple subcarriers during communication of the packet. Other embodiments are described and claimed.

公开(公告)号：US08675723B2

公开(公告)日：2014-03-18

申请号：US13027710

申请日：2011-02-15

申请人： DoHan Kim ,  Beom kon Kim ,  Sergey Zhidkov

发明人： DoHan Kim ,  Beom kon Kim ,  Sergey Zhidkov

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  H04L25/03203 ,  H04L2025/03382 ,  H04L2025/03484 ,  H04L2025/03617 ,  H04L2025/037

摘要： A symbol sequence corresponding to a vestigial sideband (VSB) signal is divided into a plurality of sections, respective ones of which correspond to respective time periods. Individual ones of the sections are recursively adaptively equalized to produce respective equalized sections. A bit stream is constructed from the equalized sections.

摘要翻译： 对应于残留边带（VSB）信号的符号序列被划分为多个部分，其中各个对应于各个时间段。 这些部分中的各个部分被递归地自适应地均衡以产生相应的相等部分。 从均衡部分构建位流。

公开(公告)号：US20140016692A1

公开(公告)日：2014-01-16

申请号：US13932561

申请日：2013-07-01

申请人： Rambus Inc.

发明人： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

摘要： A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

摘要翻译： 设备实现基于边缘的部分响应判决反馈均衡的数据接收。 在一个示例性实施例中，该设备实现一个抽头权重适配器电路，其设置用于调整接收到的数据信号的抽头权重。 抽头重量适配器电路基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样的数据信号。 时钟发生电路产生边沿时钟信号，以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。