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    LOOKUP TABLE OPTIMIZATION FOR HIGH SPEED TRANSMIT FEED-FORWARD EQUALIZATION LINK
    1.
    发明公开
    LOOKUP TABLE OPTIMIZATION FOR HIGH SPEED TRANSMIT FEED-FORWARD EQUALIZATION LINK 审中-公开

    公开(公告)号：US20240214246A1

    公开(公告)日：2024-06-27

    申请号：US18086960

    申请日：2022-12-22

    申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    发明人： Pradeep Jayaraman ,  Karthik Gopalakrishnan ,  Andrew Egli

    IPC分类号： H04L25/03 ,  H04L25/49

    CPC分类号： H04L25/03038 ,  H04L25/4917 ,  H04L2025/03471

    摘要： A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.

    APPARATUSES AND METHODS FOR REDUCING DATA PORT DELAY
    2.
    发明公开
    APPARATUSES AND METHODS FOR REDUCING DATA PORT DELAY 审中-公开

    公开(公告)号：US20240080229A1

    公开(公告)日：2024-03-07

    申请号：US17948717

    申请日：2022-09-20

    申请人： Mellanox Technologies, Ltd.

    发明人： Elad Mentovich ,  Avraham Ganor ,  Juan Jose Vegas Olmos ,  Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos

    IPC分类号： H04L25/03

    CPC分类号： H04L25/03038 ,  H04L2025/03815

    摘要： Systems, methods, apparatuses, and computer program products for reducing data port downtime are provided. An example network interface device of the present disclosure includes a first data port and a second data port. The network interface device performs a first link training process associated with the first data port coupled to a first communication link to determine a first communication parameter set for the first communication link. The network interface device then deactivates the first data port and performs a second link training process associated the second data port coupled to a second communication link to determine a second communication parameter set. Based on a network usage parameter set associated with a data plane of the network interface device, the network interface device determines whether to activate the first data port concurrently with the second data port.

    FEEDFORWARD JITTER CORRECTION
    3.
    发明公开
    FEEDFORWARD JITTER CORRECTION 审中-公开

    公开(公告)号：US20230421349A1

    公开(公告)日：2023-12-28

    申请号：US17848148

    申请日：2022-06-23

    申请人： Mellanox Technologies, Ltd.

    发明人： Johan Jacob Mohr

    IPC分类号： H04L7/033 ,  H04L25/03 ,  H04L7/00

    CPC分类号： H04L7/0331 ,  H04L25/03038 ,  H04L7/0025

    摘要： Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

    VARIABLE RESOLUTION DIGITAL EQUALIZATION
    6.
    发明申请
    VARIABLE RESOLUTION DIGITAL EQUALIZATION 审中-公开

    公开(公告)号：US20180167076A1

    公开(公告)日：2018-06-14

    申请号：US15818434

    申请日：2017-11-20

    申请人： Rambus Inc.

    发明人： Masum Hossain ,  Kenneth C. Dyer ,  Nhat Nguyen ,  Shankar Tangirala

    IPC分类号： H03M1/00 ,  H04L25/03

    CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/145 ,  H03M1/365 ,  H04L25/03 ,  H04L25/03038

    摘要： A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

    EQUALIZATION IN HIGH SPEED LINKS THROUGH IN-SITU CHANNEL ESTIMATION
    10.
    发明申请
    EQUALIZATION IN HIGH SPEED LINKS THROUGH IN-SITU CHANNEL ESTIMATION 有权

    公开(公告)号：US20170222840A1

    公开(公告)日：2017-08-03

    申请号：US15230222

    申请日：2016-08-05

    申请人： Samsung Display Co., Ltd.

    发明人： Gaurav Malhotra ,  Jalil Kamali

    IPC分类号： H04L25/03

    CPC分类号： H04L25/03885 ,  H04L25/0212 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343

    摘要： A method for estimating performance of a serial communication channel using processing circuits. The channel is configured to transmit a binary input stream from a transmitting end to an output stream at a receiving end. The method includes modeling by the processing circuits the channel at the receiving end as a first finite impulse response (FIR) system. The modeling includes estimating a cursor pulse response of the first FIR system by analyzing the output stream received at the receiving end, and estimating one or more pre-cursor or post-cursor pulse responses of the first FIR system from the received output stream using the estimated cursor pulse response. The method further includes determining by the processing circuits a performance metric by using the estimated one or more pre-cursor or post-cursor pulse responses.