公开(公告)号：US20220292035A1

公开(公告)日：2022-09-15

申请号：US17827271

申请日：2022-05-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiang Zhu ,  Fei Luo ,  Jiankang Li ,  Yulong Ma

IPC: G06F13/362 ,  G06F13/40 ,  G06F13/42

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

公开(公告)号：US20210073154A1

公开(公告)日：2021-03-11

申请号：US16952350

申请日：2020-11-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiang Zhu ,  Fei Luo ,  Jiankang Li ,  Yulong Ma

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.