公开(公告)号：US10958413B2

公开(公告)日：2021-03-23

申请号：US16533365

申请日：2019-08-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiankang Li ,  Jun Yu ,  Jiang Zhu ,  Fei Luo

IPC: H03H7/30 ,  H04L7/033 ,  H04L1/00 ,  H04L7/00 ,  H04L25/03 ,  H04L29/06

Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.

公开(公告)号：US20210065757A1

公开(公告)日：2021-03-04

申请号：US17097680

申请日：2020-11-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jun Yu ,  Guoyu Wang ,  Jiankang Li ,  You Li ,  Ruihui Hong

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

公开(公告)号：US11347669B2

公开(公告)日：2022-05-31

申请号：US16952350

申请日：2020-11-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiang Zhu ,  Fei Luo ,  Jiankang Li ,  Yulong Ma

IPC: G06F13/362 ,  G06F13/40 ,  G06F13/42

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

公开(公告)号：US20230420900A1

公开(公告)日：2023-12-28

申请号：US18466835

申请日：2023-09-14

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zongxun Chen ,  Jiankang Li ,  Huan Pei ,  Jiang Zhu

IPC: H01R33/76 ,  H01R13/652 ,  H01R12/57 ,  H01R12/71 ,  H01R13/6587

CPC classification number: H01R33/7664 ,  H01R13/652 ,  H01R12/57 ,  H01R12/716 ,  H01R13/6587

Abstract: An electronic assembly includes a first electronic component, a second electronic component, and an electrical connector connecting the first electronic component and the second electronic component. The electrical connector includes a first multilayer circuit board and a terminal that includes a plurality of signal terminals and a plurality of ground terminals. Each signal terminal is electrically connected to a signal interface of the first electronic component and a signal interface of the second electronic component. Signal terminals configured to transmit a same signal form one group of signal terminals, and at least one ground terminal is disposed between two adjacent groups of signal terminals. The first multilayer circuit board includes at least one layer of first ground copper sheet. The first electronic component includes a second multilayer circuit board, and the second multilayer circuit board includes at least one layer of second ground copper sheet.

公开(公告)号：US11430494B2

公开(公告)日：2022-08-30

申请号：US17097680

申请日：2020-11-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jun Yu ,  Guoyu Wang ,  Jiankang Li ,  You Li ,  Ruihui Hong

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

公开(公告)号：US20240214245A1

公开(公告)日：2024-06-27

申请号：US18599570

申请日：2024-03-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Junping Luo ,  Wei Pan ,  Er Nie ,  Jiankang Li

IPC: H04L25/03

CPC classification number: H04L25/03 ,  H04L25/03006 ,  H04L2025/03777

Abstract: A transmitter equalization parameter evaluation method and an apparatus are provided. The method provided in this application is used for evaluating a transmitter equalization parameter of a high-speed interface in a first device, and the method is performed by a second device connected to the first device over a communication link. The second device first detects a status of the communication link between the first device and the second device, where the communication link is constructed through the high-speed interface in the first device. When determining that the communication link is idle, the second device performs a transmitter equalization parameter evaluation process of the high-speed interface in the first device based on the communication link. When the communication link is idle, the transmitter equalization parameter evaluation process of the high-speed interface in the first device is started. This ensures efficiency of transmitter equalization parameter evaluation.

公开(公告)号：US11973856B2

公开(公告)日：2024-04-30

申请号：US17321707

申请日：2021-05-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao Li ,  Fei Luo ,  Jiankang Li ,  Jiang Zhu ,  Jieping Zeng

IPC: H04L7/00 ,  G06F13/42

CPC classification number: H04L7/005 ,  G06F13/4265 ,  G06F2213/0026 ,  G06F2213/0042

Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

公开(公告)号：US20240097947A1

公开(公告)日：2024-03-21

申请号：US18521508

申请日：2023-11-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shibin Xu ,  Kejian Wang ,  Fei Luo ,  Jiankang Li

IPC: H04L25/03 ,  H04L1/00

CPC classification number: H04L25/03343 ,  H04L1/0023 ,  H04L1/0033

Abstract: Embodiments of this application disclose a data interface equalization adjustment method and apparatus, a device, and a storage medium, and relate to the field of data interface technologies. The method includes: A second device determines equalization parameter indication information of a first transmitter TX on a first data interface. The second device sends a first equalization training sequence block ETSB to a corresponding RX on the first data interface through a TX on a second data interface, where the first ETSB carries the equalization parameter indication information and equalization target indication information, and the equalization target indication information indicates that the first TX is an equalization target. The first device determines the equalization target to be the first TX based on the equalization target indication information, and adjusts an equalization parameter of the first TX to an equalization parameter indicated by the equalization parameter indication information.

公开(公告)号：US11921660B2

公开(公告)日：2024-03-05

申请号：US17827271

申请日：2022-05-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiang Zhu ,  Fei Luo ,  Jiankang Li ,  Yulong Ma

IPC: G06F13/40 ,  G06F13/362 ,  G06F13/42

CPC classification number: G06F13/362 ,  G06F13/4022 ,  G06F13/4221

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

公开(公告)号：US11748294B2

公开(公告)日：2023-09-05

申请号：US17315715

申请日：2021-05-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao Li ,  Fei Luo ,  Jiankang Li ,  Jie Wan ,  Gongxian Jia

IPC: G06F13/42 ,  G06F13/40 ,  H04L25/03

CPC classification number: G06F13/423 ,  G06F13/4068 ,  H04L25/03885

Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.