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    Associative memory system with match,no match and multiple match resolution
    11.
    发明授权
    Associative memory system with match,no match and multiple match resolution 失效
    具有匹配，无匹配和多个匹配分辨率的相关记忆系统

    公开(公告)号：US3602899A

    公开(公告)日：1971-08-31

    申请号：US3602899D

    申请日：1969-06-20

    Applicant: IBM

    Inventor： LINDQUIST ARWIN B ,  PRICER WILBUR D ,  SEEBER ROBERT R

    IPC: G11C15/04 ,  G11C15/00

    CPC classification number: G11C15/04

    Abstract: An associative memory matrix having a writable portion made up of bistable memory cells and a read-only portion made up of monostable memory cells. The memory may be used as a conventional memory by placing an address in the address field of an entry register, masking out all other bits and performing a match interrogation with the unmasked bits. Since the contents of the address portion (read-only memory) of each stored word are unique, the interrogation results in a single match at the location containing the address sought. Included is a circuit for determining whether no match, one match, or a multiple match has occurred.

    Centralized crosspoint switching unit
    12.
    发明授权
    Centralized crosspoint switching unit 失效
    集中式切换开关单元

    公开(公告)号：US3601807A

    公开(公告)日：1971-08-24

    申请号：US3601807D

    申请日：1969-01-13

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  PRICER WILBUR D

    IPC: G06F13/40 ,  H04Q5/14 ,  H04M3/22

    CPC classification number: G06F13/4022

    Abstract: An input/output interface switching apparatus for switching I/O interfaces connecting I/O control units between channels. A matrix of transistor cross-point switches is provided for attaching one or more strings of control units to one or more channels. These strings of control unit are switched between the channels under configuration control. The cross-points are arranged so that a single failure within one interface affects at most only the channel to which the interface is associated. The switching matrix is physically centralized to minimize the number of I/O interface cables and connectors. The switching functions are, however, logically decentralized from a reliability standpoint so that a single component failure does not result in total switching system failure.

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