公开(公告)号：US20150169488A1

公开(公告)日：2015-06-18

申请号：US14132831

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  David Astrom

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F2211/002

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract translation: 总线驱动器电路可以包括第一和第二电路节点，其中第一电路节点可操作地耦合到总线线路，这导致第一和第二电路节点之间的总线电容。 开关电路耦合到第一电路节点并被配置为在第一和第二电路节点之间施加输出电压。 从而当控制信号表示主导状态时，总线电容被充电。 放电电路包括至少一个电阻器。 放电电路耦合在第一和第二电路节点之间，并且被配置为当控制信号指示隐性状态时允许总线电容经由电阻放电。 开关电路还被配置为提供用于在从显性状态到隐性状态的过渡期期间对总线电容放电的临时电流通路。

公开(公告)号：US08975915B2

公开(公告)日：2015-03-10

申请号：US13631925

申请日：2012-09-29

Applicant: Infineon Technologies AG

Inventor： David Astrom ,  Daniel Mandler

IPC: H03K19/003

CPC classification number: H04L25/0272 ,  H04L12/40006 ,  H04L12/40032 ,  H04L25/0264 ,  H04L2012/40215 ,  H04L2012/40234 ,  H04L2012/40241 ,  H04L2012/40273

Abstract: A driver circuit for a digital signal transmitting bus includes a main switch. The main switch is connected to the bus, is controllable by the digital signal to be transmitted, and has one on-switching state in which it has maximum electrical conductivity, one off-switching state in which it has minimum electrical conductivity and at least one intermediate switching state with an electrical conductivity between the minimum and maximum conductivity. The digital signal has a first logic state and a second logic state, the first logic state controls the main switch to be in the on-switching state and the second logic state controls the main switch to be in the off-switching state. The main switch is in the intermediate switching state during switching from the on-switching state to the off-switching state and/or vice versa.

Abstract translation: 数字信号发送总线的驱动电路包括主开关。 主开关连接到总线，由要传输的数字信号控制，并具有一个导通状态，其中它具有最大的导电性，一个断开状态，其中具有最小导电性和至少一个 具有最小和最大导电率之间的导电性的中间开关状态。 数字信号具有第一逻辑状态和第二逻辑状态，第一逻辑状态控制主开关处于导通状态，第二逻辑状态控制主开关处于断开状态。 在从开关状态切换到断开状态和/或反之亦然时，主开关处于中间开关状态。