公开(公告)号：US09417983B2

公开(公告)日：2016-08-16

申请号：US13908702

申请日：2013-06-03

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  Paul Wallner ,  Thomas Rickes

IPC: G06F13/36 ,  H02H7/09 ,  H02H3/00 ,  H02H9/08 ,  G06F11/30 ,  G06F13/40

CPC classification number: G06F11/3027 ,  G06F11/3062 ,  G06F13/4027 ,  G06F13/4072

Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Abstract translation: 描述了用于驱动总线的电路，其包括在总线终端处耦合到至少一个信号线的至少一个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到至少一个分支的电流检测单元，其被配置为检测通过至少一个分支的电流。 电路还包括耦合到电流检测单元和发送数据输入两者的过电流确定单元。 过电流确定单元被配置为基于至少一个分支处的电流和发送数据输入处的数据来确定至少一个分支处的过电流状况。

公开(公告)号：US09172235B2

公开(公告)日：2015-10-27

申请号：US13908770

申请日：2013-06-03

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  Paul Wallner ,  Thomas Rickes

IPC: H02H3/08 ,  H04L25/02

CPC classification number: H02H3/08 ,  H04L25/0272 ,  H04L25/0282

Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.

Abstract translation: 描述了用于驱动总线的电路，其包括在总线的终止处耦合到至少一个信号线的多个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到发射数据输入的过电流验证单元，其被配置为至少部分地基于发射数据输入端的数据来验证在多个分支的第一支路处检测到的过电流状况 。 电路还包括耦合到过电流验证单元的分支控制单元，其被配置为响应于在第一分支处的验证过电流状况来禁用多个分支中的至少一个分支。

公开(公告)号：US20140359190A1

公开(公告)日：2014-12-04

申请号：US13908702

申请日：2013-06-03

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  Paul Wallner ,  Thomas Rickes

IPC: G06F11/30 ,  G06F13/40

CPC classification number: G06F11/3027 ,  G06F11/3062 ,  G06F13/4027 ,  G06F13/4072

Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Abstract translation: 描述了用于驱动总线的电路，其包括在总线终端处耦合到至少一个信号线的至少一个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到至少一个分支的电流检测单元，其被配置为检测通过至少一个分支的电流。 电路还包括耦合到电流检测单元和发送数据输入两者的过电流确定单元。 过电流确定单元被配置为基于至少一个分支处的电流和发送数据输入处的数据来确定至少一个分支处的过电流状况。

公开(公告)号：US09495317B2

公开(公告)日：2016-11-15

申请号：US14132831

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  David Astrom

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F2211/002

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract translation: 总线驱动器电路可以包括第一和第二电路节点，其中第一电路节点可操作地耦合到总线线路，这导致第一和第二电路节点之间的总线电容。 开关电路耦合到第一电路节点并被配置为在第一和第二电路节点之间施加输出电压。 从而当控制信号表示主导状态时，总线电容被充电。 放电电路包括至少一个电阻器。 放电电路耦合在第一和第二电路节点之间，并且被配置为当控制信号指示隐性状态时允许总线电容经由电阻放电。 开关电路还被配置为提供用于在从显性状态到隐性状态的过渡期期间对总线电容放电的临时电流通路。

公开(公告)号：US20150169488A1

公开(公告)日：2015-06-18

申请号：US14132831

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  David Astrom

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F2211/002

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract translation: 总线驱动器电路可以包括第一和第二电路节点，其中第一电路节点可操作地耦合到总线线路，这导致第一和第二电路节点之间的总线电容。 开关电路耦合到第一电路节点并被配置为在第一和第二电路节点之间施加输出电压。 从而当控制信号表示主导状态时，总线电容被充电。 放电电路包括至少一个电阻器。 放电电路耦合在第一和第二电路节点之间，并且被配置为当控制信号指示隐性状态时允许总线电容经由电阻放电。 开关电路还被配置为提供用于在从显性状态到隐性状态的过渡期期间对总线电容放电的临时电流通路。

公开(公告)号：US20140355158A1

公开(公告)日：2014-12-04

申请号：US13908770

申请日：2013-06-03

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  Paul Wallner ,  Thomas Rickes

IPC: H02H3/08

CPC classification number: H02H3/08 ,  H04L25/0272 ,  H04L25/0282

Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.

Abstract translation: 描述了用于驱动总线的电路，其包括在总线的终止处耦合到至少一个信号线的多个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到发射数据输入的过电流验证单元，其被配置为至少部分地基于发射数据输入端的数据来验证在多个分支的第一支路处检测到的过电流状况 。 电路还包括耦合到过电流验证单元的分支控制单元，其被配置为响应于在第一分支处的验证过电流状况来禁用多个分支中的至少一个分支。