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    CLOCK MANAGER MONITORING FOR TIME SYNCHRONIZED NETWORKS
    16.
    发明申请
    CLOCK MANAGER MONITORING FOR TIME SYNCHRONIZED NETWORKS 有权

    公开(公告)号：US20220303034A1

    公开(公告)日：2022-09-22

    申请号：US17829042

    申请日：2022-05-31

    Applicant: INTEL CORPORATION

    Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Manoj Sastry ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang

    IPC: H04J3/06

    Abstract: Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

    Active attack detection in autonomous vehicle networks
    17.
    发明授权
    Active attack detection in autonomous vehicle networks 有权

    公开(公告)号：US11444961B2

    公开(公告)日：2022-09-13

    申请号：US16723142

    申请日：2019-12-20

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Vuk Lesi ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Manoj Sastry ,  Liuyang Yang ,  Xiruo Liu

    IPC: G06F11/00 ,  H04L9/40 ,  G05B19/042 ,  G05D1/00

    Abstract: Systems, methods, computer-readable storage media, and apparatuses to provide active attack detection in autonomous vehicle networks. An apparatus may comprise a plurality of electronic control units communicably coupled by a network, and logic, at least a portion of which is implemented in hardware, the logic to: receive an indication from a first electronic control unit (ECU) of the plurality of ECUs specifying to transmit a first data frame via the network, determine, based on a message identifier (ID) of the first ECU, whether a transmit window for the first ECU is open, and permit the first ECU to transmit the first data frame via the network based on a determination that the transmit window for the first ECU is open.

    Hardware random forest: low latency, fully reconfigurable ensemble classification
    19.
    发明授权
    Hardware random forest: low latency, fully reconfigurable ensemble classification 有权

    公开(公告)号：US11409286B2

    公开(公告)日：2022-08-09

    申请号：US16718495

    申请日：2019-12-18

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Christopher Gutierrez ,  Shabbir Ahmed ,  Manoj Sastry ,  Liuyang Yang ,  Xiruo Liu

    IPC: G05D1/00 ,  G06N5/04 ,  G06F16/901 ,  G06K9/62

    Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.

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