ARCHITECTURE FOR REDUCTION OF RF INTERFERENCE ON CLOCK CIRCUITS

    公开(公告)号:US20250007501A1

    公开(公告)日:2025-01-02

    申请号:US18214885

    申请日:2023-06-27

    Abstract: An apparatus includes an oscillator circuit and a low-pass filter circuit coupled to an output terminal of the oscillator circuit. The apparatus further includes a first digital signal generator coupled to at least one of an output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit and a second digital signal generator coupled to at least one of the output terminal of the low-pass filter circuit and the output terminal of the oscillator circuit. The second digital signal generator generates a second digital clock signal based on a non-differential signal output of the oscillator circuit. The apparatus further includes a radio frequency interference (RFI) detection circuit coupled to the first digital signal generator and the second digital signal generator. The RFI detection circuit detects RFI associated with the non-differential signal output of the oscillator circuit.

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