公开(公告)号：US09893881B2

公开(公告)日：2018-02-13

申请号：US14753987

申请日：2015-06-29

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Siddhartha Chhabra ,  Evgeny Zhyvov ,  Eugene M. Kishinevsky ,  Men Long

IPC: H04L9/06 ,  G06F21/72 ,  G06F21/76

CPC classification number: H04L9/0637 ,  G06F21/57 ,  G06F21/72 ,  G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

Abstract: A processing or memory device may include a first encryption pipeline to encrypt and decrypt data with a first encryption mode and a second encryption pipeline to encrypt and decrypt data with a second encryption mode, wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline. A controller (and/or other logic) may direct selection of encrypted (or decrypted) data from the first and second encryption pipelines responsive to a region of memory to which a physical address of a memory request is directed. The result of the selection may result in bypassing encryption/decryption or encrypting/decrypting the data according to the first encryption mode or the second encryption mode. More than two encryption modes are envisioned.

公开(公告)号：US20170063532A1

公开(公告)日：2017-03-02

申请号：US14753987

申请日：2015-06-29

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Siddhartha Chhabra ,  Evgeny Zhyvov ,  Eugene M. Kishinevsky ,  Men Long

IPC: H04L9/06 ,  G06F21/76 ,  G06F21/72

CPC classification number: H04L9/0637 ,  G06F21/57 ,  G06F21/72 ,  G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

Abstract: A processing or memory device may include a first encryption pipeline to encrypt and decrypt data with a first encryption mode and a second encryption pipeline to encrypt and decrypt data with a second encryption mode, wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline. A controller (and/or other logic) may direct selection of encrypted (or decrypted) data from the first and second encryption pipelines responsive to a region of memory to which a physical address of a memory request is directed. The result of the selection may result in bypassing encryption/decryption or encrypting/decrypting the data according to the first encryption mode or the second encryption mode. More than two encryption modes are envisioned.

Abstract translation: 处理或存储设备可以包括用第一加密模式加密和解密数据的第一加密流水线和用第二加密模式对数据进行加密和解密的第二加密流水线，其中第一加密流水线和第二加密流水线共享一个 ，用于由第一加密流水线和第二加密流水线执行的大多数加密和解密操作的共享流水线。 响应于存储器请求的物理地址所针对的存储器区域，控制器（和/或其他逻辑）可以直接从第一和第二加密流水线中选择加密（或解密的）数据。 选择的结果可能导致绕过加密/解密或者根据第一加密模式或第二加密模式对数据进行加密/解密。 设想了两种以上的加密模式。

公开(公告)号：US08990662B2

公开(公告)日：2015-03-24

申请号：US13631937

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

IPC: H03M13/00 ,  G06F11/14

CPC classification number: G06F11/1443 ,  H04L1/20 ,  H04L1/242

Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

Abstract translation: 弹性沟通技巧。 数据路径存储要通过链接发送到接收节点的数据。 输出级耦合在数据路径和链路之间。 输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。 错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。 响应于检测到错误，错误检测电路使得​​输出级发送通过链路发送的数据的副本。