公开(公告)号：US20190042248A1

公开(公告)日：2019-02-07

申请号：US15941526

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Dennis Ryan BRADFORD ,  Jesus CORBAL ,  Brian HICKMANN ,  Rohan SHARMA

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to a method and apparatus for efficient matrix transpose. In one example, a processor to execute a matrix transpose instruction includes fetch circuitry to fetch the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, a (N×M) load buffer, decode circuitry to decode the fetched matrix transpose instruction, and execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the specified source matrix: fetch and buffer N elements of the row in a load register, and cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of the load buffer, and the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the load buffer.

公开(公告)号：US20240111533A1

公开(公告)日：2024-04-04

申请号：US18534012

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Dan BAUM ,  Alexander F. HEINECKE ,  Elmoustaha OULD-AHMED-VALL ,  Yuri GEBIL ,  Raanan SADE

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US20220300286A1

公开(公告)日：2022-09-22

申请号：US17833643

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Stanislav SHWARTSMAN

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

公开(公告)号：US20220291926A1

公开(公告)日：2022-09-15

申请号：US17706413

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Stanislav SHWARTSMAN ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Dan BAUM ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

公开(公告)号：US20220236989A1

公开(公告)日：2022-07-28

申请号：US17587637

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Dan BAUM ,  Alexander HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.

公开(公告)号：US20210096822A1

公开(公告)日：2021-04-01

申请号：US17121155

申请日：2020-12-14

Applicant: INTEL CORPORATION

Inventor： Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Simon RUBANOVICH ,  Amit GRADSTEIN ,  Zeev SPERBER ,  Bret TOLL ,  Jesus CORBAL ,  Christopher J. HUGHES ,  Alexander F. HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F7/78 ,  G06F9/30 ,  G06F15/173 ,  G06F9/38

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transpose rectangular tiles. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first destination, second destination, first source, and second source matrices, the specified opcode to cause the processor to process each of the specified source and destination matrices as a rectangular matrix, decode circuitry to decode the fetched rectangular matrix transpose instruction, and execution circuitry to respond to the decoded rectangular matrix transpose instruction by transposing each row of elements of the specified first source matrix into a corresponding column of the specified first destination matrix and transposing each row of elements of the specified second source matrix into a corresponding column of the specified second destination matrix.

公开(公告)号：US20210081200A1

公开(公告)日：2021-03-18

申请号：US16642766

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Venkateswara R. MADDURI ,  Carl MURRAY ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Robert VALENTINE ,  Jesus CORBAL

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

公开(公告)号：US20210072985A1

公开(公告)日：2021-03-11

申请号：US16642778

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Venkateswara R. MADDURI ,  Carl MURRAY ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Robert VALENTINE ,  Jesus CORBAL

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

公开(公告)号：US20200233665A1

公开(公告)日：2020-07-23

申请号：US16487747

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Dan BAUM ,  Alexander HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F17/16

Abstract: Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.

公开(公告)号：US20200065352A1

公开(公告)日：2020-02-27

申请号：US16487421

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Mark J. CHARNEY ,  Elmoustapha OULD-AHMED-VALL ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Bret L. TOLL ,  Raanan SADE ,  Igor YANOVER ,  Yuri GEBIL ,  Rinat RAPPOPORT ,  Stanislav SHWARTSMAN ,  Menachem ADELMAN ,  Simon RUBANOVICH

IPC: G06F17/16 ,  G06F9/30

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.