公开(公告)号：US20230136268A1

公开(公告)日：2023-05-04

申请号：US18086634

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes data buffer to memory chip write training circuitry. The data buffer to memory chip write training circuitry to send MDQ/MDQS phase relationship programming information, write commands and read commands to the data buffer chips for multiple write training iterations without a host memory controller having provided the MDQ/MDQS phase relationship programming information, the write commands and the read commands to the data buffer to memory chip write training circuitry.

公开(公告)号：US20220301608A1

公开(公告)日：2022-09-22

申请号：US17830118

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

公开(公告)号：US20220276958A1

公开(公告)日：2022-09-01

申请号：US17747950

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  George VERGIS ,  Tonia M. ROSE ,  John R. GOLES ,  John V. LOVELACE

IPC: G06F12/06

Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

公开(公告)号：US20180181336A1

公开(公告)日：2018-06-28

申请号：US15392912

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： John V. LOVELACE ,  Sreenivas MANDAVA ,  Debaleena DAS

IPC: G06F3/06

CPC classification number: G06F21/79 ,  G06F11/1048 ,  G06F2221/2143

Abstract: A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.