公开(公告)号：US20160098366A1

公开(公告)日：2016-04-07

申请号：US14967226

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  John V. LOVELACE ,  Murugasamy M. NACHIMUTHU ,  Tuan M. QUACH

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register

Abstract translation: 提供了一种用于对存储器模块中的寄存器进行编码的方法和装置的方法和装置。 通过总线将模式寄存器命令发送到存储器模块，在对存储器模块的总线进行总线操作的训练之前对存储器模块的初始化进行编程，以对存储器模块中的多个模式寄存器中的一个进行编程，其中模式寄存器 命令指示模式寄存器之一，并包括指示模式寄存器的数据

公开(公告)号：US20230017161A1

公开(公告)日：2023-01-19

申请号：US17950663

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G11C7/10 ,  G11C8/18

Abstract: System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

公开(公告)号：US20220300197A1

公开(公告)日：2022-09-22

申请号：US17749916

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

IPC: G06F3/06

Abstract: Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.

公开(公告)号：US20210382640A1

公开(公告)日：2021-12-09

申请号：US17411960

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Sreenivas MANDAVA ,  John V. LOVELACE

IPC: G06F3/06 ,  G06F11/10

Abstract: Initialization of a memory can have different phases, first initializing a portion of memory for BIOS (basic input/output system) and initializing other portions of memory while the BIOS is operating. The initialization of the memory can be performed by the error scrub engine. In a first mode of operation, the scrub engine can initialize memory locations, then transition to performing scrub operations.

公开(公告)号：US20190034365A1

公开(公告)日：2019-01-31

申请号：US15829524

申请日：2017-12-01

Applicant: Intel Corporation

Inventor： John V. LOVELACE ,  Christina JUE

IPC: G06F13/16 ,  G06F11/10 ,  G06F9/30

Abstract: Techniques for training a command/address (C/A) bus, including training internal command/address (C/A) signal lines of a memory module are described. In one example, a method of training a C/A bus involves a memory controller transmitting a first command to a DRAM with parity checking enabled, the first command to include valid parity and chip select asserted. The memory controller transmits commands in cycles before and after the first command to at least one DRAM with parity checking disabled, the commands to include invalid parity and chip select asserted. In response to detecting a parity error, the memory controller modifies a timing parameter to adjust timing for the internal C/A signal lines of the memory module.

公开(公告)号：US20150325281A1

公开(公告)日：2015-11-12

申请号：US14639025

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  John V. LOVELACE ,  Benjamin T. TYSON

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.

Abstract translation: 存储器控制器将控制信号发送到存储器模块，其中存储器控制器将时钟信号连续发送到存储器模块。 存储器控制器通过迭代地分析选通信号来确定相对于时钟信号对控制信号的调整。

公开(公告)号：US20230125412A1

公开(公告)日：2023-04-27

申请号：US18086639

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

IPC: G11C7/10 ,  G11C7/22

Abstract: An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

公开(公告)号：US20200065266A1

公开(公告)日：2020-02-27

申请号：US16529700

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  John V. LOVELACE ,  John R. GOLES

IPC: G06F13/16 ,  G06F1/10

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

公开(公告)号：US20190095361A1

公开(公告)日：2019-03-28

申请号：US15718346

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  John V. LOVELACE ,  John R. GOLES

IPC: G06F13/16 ,  G06F1/10

CPC classification number: G06F13/1663 ,  G06F1/10 ,  G06F13/1689

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

公开(公告)号：US20180069692A1

公开(公告)日：2018-03-08

申请号：US15255564

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Ying ZHOU ,  John V. LOVELACE ,  Alberto David PEREZ

IPC: H04L7/033 ,  H04L7/08 ,  H04L7/00

CPC classification number: H04L7/0041 ,  G11C7/00 ,  G11C29/023 ,  G11C29/028 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0331

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.