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公开(公告)号：US11024007B2
公开(公告)日：2021-06-01
申请号：US17032709
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Robert M. Toth , Bjorn Johnsson , Jon N. Hasselgren
Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
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12.发明申请公开(公告)号：US20190172246A1
公开(公告)日：2019-06-06
申请号：US16155314
申请日：2018-10-09
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Jon N. Hasselgren
Abstract: It is presented a method for improving performance of generation of digitally represented graphics. Said method comprises the steps of: selecting (440) a tile comprising fragments to process; executing (452) a culling program for the tile, the culling program being replaceable; and executing a set of instructions, selected from a plurality of sets of instructions based on an output value of the culling program, for each of a plurality of subsets of the fragments. A corresponding display adapter and computer program product are also presented.
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公开(公告)号：US20190130634A1
公开(公告)日：2019-05-02
申请号：US16233449
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Jon N. Hasselgren , Carl J. Munkberg
Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.
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公开(公告)号：US10089964B2
公开(公告)日：2018-10-02
申请号：US14975400
申请日：2015-12-18
Applicant: INTEL CORPORATION
Inventor： Jon N. Hasselgren
Abstract: Embodiments provide for a graphics processing apparatus comprising a graphics processing unit including bounding volume logic to encode a first bounding volume and a second bounding volume for a bounding volume hierarchy, wherein the first bounding volume is to be encoded at a higher numerical precision relative to the second bounding volume and the first bounding volume encloses the second bounding volume.
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公开(公告)号：US20180075573A1
公开(公告)日：2018-03-15
申请号：US15260570
申请日：2016-09-09
Applicant: Intel Corporation
Inventor： Robert M. Toth , Carl J. Munkberg , Jon N. Hasselgren
CPC classification number: G06T1/60 , G06T1/20 , G06T15/005 , G06T2210/08
Abstract: Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US09916682B2
公开(公告)日：2018-03-13
申请号：US14925325
申请日：2015-10-28
Applicant: Intel Corporation
Inventor： Rahul P. Sathe , Bimal Poddar , Jon N. Hasselgren
CPC classification number: G06T15/80 , G06K9/4604 , G06K9/4671 , G06K2009/4666 , G06T15/005 , G06T15/04 , G06T2200/04 , G06T2200/28 , G06T2210/36 , G06T2215/16
Abstract: The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.
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公开(公告)号：US09734597B2
公开(公告)日：2017-08-15
申请号：US14975501
申请日：2015-12-18
Applicant: INTEL CORPORATION
Inventor： Tomas G. Akenine-Moller , Jon N. Hasselgren , Jim K. Nilsson
CPC classification number: G06T9/00 , G06T9/004 , G06T15/005 , G06T15/04 , G06T15/80
Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.
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公开(公告)号：US20170124742A1
公开(公告)日：2017-05-04
申请号：US14926741
申请日：2015-10-29
Applicant: Intel Corporation
Inventor： Jon N. Hasselgren , Tomas G. Akenine-Moller , Carl J. Munkberg , Franz P. Clarberg , Jim K. Nilsson
Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.
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公开(公告)号：US20150287238A1
公开(公告)日：2015-10-08
申请号：US14688107
申请日：2015-04-16
Applicant: Intel Corporation
Inventor： Tomas G. Akenine-Moller , Carl J. Munkberg , Jon N. Hasselgren , Robert M. Toth
Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
Abstract translation: 可以通过剔除要被渲染的三角形不可见的透镜上的半空间区域来光栅化景深。 然后，内部测试仅对剩余的未被空白的半空间区域进行。 要渲染的三角形和正在处理的瓷砖之间的分离平面可用于定义半空间区域。
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公开(公告)号：US09111392B2
公开(公告)日：2015-08-18
申请号：US13721163
申请日：2012-12-20
Applicant: Intel Corporation
Inventor： Magnus Andersson , Carl J. Munkberg , Tomas G. Akenine-Moller , Jon N. Hasselgren
Abstract: Unlike a static primitive, where the depth function is planar, the depth function for a moving and defocused triangle is a rational function in time and the lens parameters. Compact depth functions can be used to design an efficient depth buffer compressor/decompressor, which significantly lowers total depth buffer bandwidth usage. In addition, this compressor/decompressor is substantially simpler in the number of operations needed to execute, which makes it more amenable for hardware implementation than previous methods.
Abstract translation: 与静态原语不同，其中深度函数是平面的，移动和散焦三角形的深度函数是时间上的理性函数和透镜参数。 紧凑的深度功能可用于设计高效的深度缓冲压缩/解压缩器，显着降低了总深度缓冲带宽的使用。 此外，该压缩器/解压缩器在执行所需的操作数量上基本上更简单，这使得它比以前的方法更适合硬件实现。
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