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公开(公告)号:US11887563B1
公开(公告)日:2024-01-30
申请号:US18049555
申请日:2022-10-25
申请人: Heavy.AI, Inc.
发明人: Todd L. Mostak , Christopher Root
CPC分类号: G09G5/363 , G06F3/14 , G06T1/20 , G06T1/60 , G09G5/001 , G09G5/393 , G09G5/397 , G09G2340/02 , G09G2360/08
摘要: A system and method runs a query using a GPU and generates a visualization of the query using the same GPU.
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公开(公告)号:US11586835B2
公开(公告)日:2023-02-21
申请号:US17675975
申请日:2022-02-18
IPC分类号: G06F40/58 , G06V30/146 , G09G5/397 , G06T1/20
摘要: An apparatus, method, and computer readable medium for generating and displaying a dynamic language translation overlay that include accessing a frame buffer of the GPU, analyzing, in the frame buffer of the GPU, a frame representing a section of a stream of displayed data that is being displayed by a display device, based on the analyzed frame, identifying a reference patch that includes an instruction to identify an object comprising original text, based on the instruction included in the reference patch, recognizing the original text, generating translated text, generating an overlay comprising an augmentation layer, the augmentation layer including the translated text, and overlaying the overlay, onto the displayed data such that the translated text is viewable while the original text is obscured from view.
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公开(公告)号:US11567780B2
公开(公告)日:2023-01-31
申请号:US17353697
申请日:2021-06-21
申请人: Movidius Limited
发明人: David Moloney , Cormac Brick , Ovidiu Andrei Vesa , Brendan Barry
IPC分类号: G06F12/00 , G06F9/38 , G09G5/36 , G09G5/397 , G06T1/20 , G06T1/60 , G06F12/02 , G06F12/0842 , G06F3/06 , G06F12/0844
摘要: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
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公开(公告)号:US11303942B2
公开(公告)日:2022-04-12
申请号:US16879052
申请日:2020-05-20
发明人: Ashraf Nehru
IPC分类号: H04N21/2343 , H04N7/015 , H04N21/2365 , H04N7/08 , G09G5/391 , G09G5/00 , G09G5/36 , G09G5/397
摘要: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.
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公开(公告)号:US11199964B2
公开(公告)日:2021-12-14
申请号:US16961970
申请日:2018-11-06
发明人: Hye Jin Sim , Bo Eun Song , Joon Hwan Kim , Hyun Kyoung Kim , Min Wook Na , Ji Won Yoo , Hyun Do Lee , Yun Sung Jung , Hye Mi Hong
IPC分类号: G06F3/0488 , G09G3/00 , G06F3/041 , G06F3/0483 , G06F3/0485 , G09G5/14 , G09G5/397
摘要: An electronic device according to various embodiments may comprise: a first housing including a first surface and a second surface facing away from the first surface; a second housing including a third surface and a fourth surface facing away from the third surface; a folding part pivotably connecting a side surface of the first housing and a side surface of the second housing facing the side surface of the first housing; a flexible display disposed on the first and third surfaces across the folding part, having a first area corresponding to the first surface and a second area corresponding to the third surface; and a processor.
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公开(公告)号:US11175717B2
公开(公告)日:2021-11-16
申请号:US16086084
申请日:2017-03-17
发明人: Seung Jin Kim , Ji Hun Kim , Gwang Hui Lee , Sung Jun Lee , Woo Jun Jung , Min Jung Kim
IPC分类号: G09G5/36 , G06F1/3225 , G06F3/14 , G09G5/393 , G09G5/397
摘要: Various examples of the present invention relate to an electronic device comprising: a graphic buffer for storing graphic information received from an application; a frame buffer for storing the graphic information to be displayed on a display; and a processor, wherein the processor is configured to: store, in the graphic buffer, first graphic information received from a first layer; store, in the frame buffer, second graphic information received from a second layer; store, in the frame buffer, the first graphic information stored in the graphic buffer; and simultaneously display the first graphic information and the second graphic information, stored in the frame buffer, through the display functionally connected with the processor. In addition, other examples identifiable through the specification are possible.
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公开(公告)号:US20210312584A1
公开(公告)日:2021-10-07
申请号:US17353687
申请日:2021-06-21
申请人: NextLabs, Inc.
摘要: A method and system of augmenting display content in a graphical user interface environment. Content produced by a graphical user interface is augmented with additional content before the content is displayed. In an example, a security marker may be rendered on top of an existing display content using the method described to protect high-value or sensitive information.
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公开(公告)号:US11132590B2
公开(公告)日:2021-09-28
申请号:US17119531
申请日:2020-12-11
申请人: IAS Machine, LLC
摘要: An augmented reality system for procedural guidance identifies a fiducial marker object in a frame of a first field of view generated by a camera, determines a pose of the fiducial marker object, applies the fiducial marker pose to generate a first transformation between a first coordinate system of the fiducial marker object and a second coordinate system of the camera, and applies a pose of a headset to determine a second transformation between the first coordinate system and a third coordinate system of the headset.
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公开(公告)号:US11049225B2
公开(公告)日:2021-06-29
申请号:US16333507
申请日:2018-02-26
发明人: Masayuki Kozuka , Masaya Yamamoto , Toshiroh Nishio , Kazuhiko Kouno , Yoshiichiro Kashiwagi , Takeshi Hirota , Hiroshi Yahata , Yoshihiro Mori
IPC分类号: G09G5/10 , G09G5/397 , H04N19/186 , G06T5/00 , G06T11/60 , G06T5/50 , G09G5/00 , G09G5/02 , H04N5/66 , H04N5/20 , H04N21/431 , G06T11/00
摘要: A video processing system includes: an acquirer that acquires video data including a main video; a format acquirer that acquires a display format that indicates a luminance dynamic range format displayable by a video display apparatus; a generator that generates first characteristics information that indicates first dynamic luminance characteristics that correspond to the display format by using the video data when a luminance dynamic range format of the main video indicated by the video data is different from the display format, the first dynamic luminance characteristics being dynamic luminance characteristics indicating a time-dependent change in luminance characteristics of the main video; and a video transmitter that outputs the first characteristics information generated by the generator.
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公开(公告)号:US11042382B2
公开(公告)日:2021-06-22
申请号:US16444559
申请日:2019-06-18
申请人: Movidius Limited
发明人: David Moloney , Cormac Brick , Ovidiu Andrei Vesa , Brendan Barry
摘要: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
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